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1. general description the ensation base, SAA8200HL, is part of the integrated wireless audio system chip set offered by philips. this chip set enables the development of low cost wireless digital audio systems. the chip set contains: ? an integrated wireless audio baseband chip (SAA8200HL) ? an integrated wireless audio radio chip (tea7000). integrating a wireless audio link in a home theatre system to remove part of the wiring is a logical application of wireless audio transmission. a very important property of this wireless audio system is the low end-to-end (audio-in at transmit side to audio-out at receive side) system latency, which is below 20 ms. a second important property is the robustness and reliability of the wireless audio link, the SAA8200HL which is handling the signal processing and the system control enables this. furthermore, the SAA8200HL provides the ?exibility to allow designers to make trade-offs between air bit-rate, number of transported audio channels, audio formats, audio coding bit-rates, range, number of receiving-slaves and more. due to its low power consuming design, the SAA8200HL enables battery powered applications. the SAA8200HL does this all with a minimum of external components due to its high level of integration. SAA8200HL ensation base integrated wireless audio baseband rev. 02 17 october 2005 preliminary data sheet fig 1. ensation link system example using two integrated wireless audio baseband and radio ics 001aab062 baseband chip saa8200 rf chip tea7000 analog i 2 s-bus i 2 c-bus spdif gpio audio/voice in/out data in/out peripherals/ui baseband chip saa8200 rf chip tea7000 analog i 2 s-bus i 2 c-bus gpio audio/voice in/out data in/out peripherals/ui
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 2 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband together with the tea7000, the SAA8200HL can be used to implement an indoor wireless link for audio applications (system speci?c). together with an av-compliant bluetooth radio module, the SAA8200HL can be used to implement a bluetooth wireless audio functionality. the SAA8200HL enables a low power, low cost two-chip solution with a maximum amount of functions integrated on the SAA8200HL, taking into account strict time-to-market constraints. 2. features 2.1 general n programmable baseband processor and system controller for cable replacement wireless audio n supports various audio compression formats n wireless audio protocol can make trade-off between quality, number of channels, bandwidth and range n supports various transmission frequencies n high integration allows for two-chip applications n embedded rom with wireless audio software library. 2.2 hardware n audio pll and system pll n read-solomon encoder and decoder n spdif interface n low cost low power epics7b dsp core with hardware debugger and jtag interface n integrated memories: u 24/6 kwords program rom/ram (bit width: 32 bits) u 12 kwords x data ram (bit width: 24 bits) u 12/2 kwords y data rom/ram (bit width: 12 bits). n interrupt controller n dma controller n oscillator and time base unit with programmable clocks n embedded ldo regulators and dc-to-dc converters for on-chip and off-chip supply voltage needs n power control unit n power on and power off switching with battery supply n reed-solomon codec unit n serial radio interface unit n high speed uart n general purpose digital i/o block with 14 inputs, all of which generate interrupts n i 2 c-bus master/slave n i 2 c-bus for radio chip control n control 10-bit adc with four inputs
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 3 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband n two serial (i 2 s-bus/japanese) digital audio inputs with independent clocks and word-select n two serial (i 2 s-bus/japanese) digital audio outputs with shared clock and word-select n integrated 16-bit stereo dac (line output) n integrated stereo headphone ampli?er n programmable gain ampli?er (pga) (line input) n low noise microphone ampli?er (microphone input) n integrated 16-bit stereo adc n watchdog timer. 2.3 software n stereo sub band coding (sbc) encoder/decoder n stereo mpeg layer 3 (mp3) decoder n reed-solomon encoder/decoder driver n sample rate converter n i 2 c-bus master/slave driver n serial radio interface driver n rf radio chip driver n uart driver n control 10-bit adc driver n power consumption management n adc, dac and headphone driver n wireless audio protocol library. 3. applications n wireless front speakers or wireless surround speakers for home theatre n wireless indoor headphones n wireless second room audio sets n wireless headsets. 4. ordering information table 1: ordering information type number package name description version SAA8200HL lqfp100 plastic low pro?le quad ?at package; 100 leads; body 14 14 1.4 mm sot407-1
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 4 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 5. block diagram pins 7, 80 to 84 and 87 are multiplexed functions pins. fig 2. block diagram spdif i2sout_2 i2sout_1 audio dac audio adc audio pll system pll crystal oscillator i2sin_1 i2sin_2 timestamp counter pga lna headphone amplifier memories dma controller vpb bridge sri sri i2c control adc watchdog event router io config- uration system i2c 2 3 iic_ms_scl iic_ms_sda 100 1 iic_sri_scl iic_sri_sda 94 95 sri_fsync_p 29 spdif_in 72 i2sin_1_data 73 i2sin_1_ws 74 i2sin_1_bck 84 i2sin_2_data 87 i2sin_2_ws 7 i2sin_2_bck 76, 77 i2sout_ws, i2sout_bck 78 i2sout_2_data 79 i2sout_1_data 14 dac_outl 15 dac_outr 16 hp_outl 20 hp_outr 23 adc_inr 24 25 adc_inl 26 27 adc_mic_in 71 clk_out1 75 clk_out2 4 rstin_n 92 xtalh_in 91 xtalh_out sri_fsync_n 96 sri_gchclk_p 97 sri_gchclk_n 39 40 adc10b_gpa0 adc10b_gpa1 41 adc10b_gpa2 42 adc10b_gpa3 80 81 uart_nrts uart_ncts 82 uart_rxs 83 uart_txs 80 81 gpio_04 gpio_05 82 gpio_06 83 gpio_07 7 8 gpio_10 gpio_11/sri_int 9 gpio_12 10 gpio_13 47 48 gpio_03 gpio_02/mode_1 49 gpio_01/mode_0 50 55 63 gpio_00 84 gpio_08 87 gpio_09 3.3 v/1.8 v supply v bat(dcdc) v usb(dcdc) 98 sri_data_p 64 65 jtag_tdi jtag_tms 66 jtag_tdo 67 jtag_tck 68 jtag_trst_n 99 sri_data_n rsc uart epics7b hardware debugger jtag cgu audio configuration dc/dc convertor 001aab054 SAA8200HL adc_mic_pga adc_mic_lna 2
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 5 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 6. pinning information 6.1 pinning fig 3. pin con?guration SAA8200HL iic_sri_sda clk_out2 iic_ms_scl i2sin_1_bck iic_ms_sda i2sin_1_ws rstin_n i2sin_1_data v ssi1 clk_out1 v ddi1 v dde1 gpio_10/i2sin_2_bck v sse1 gpio_11/sri_int jtag_trst_n gpio_12 jtag_tck gpio_13 jtag_tdo dac_refn jtag_tms dac_refp jtag_tdi v dda(3v3_dac) v usb(dcdc) dac_outl dcdc_out3v3 hp_outr dcdc_out1v8 hp_com v bat(dcdc) v ssa(adc) v ssa(dcdc) adc_inr dcdc_play adc_inl dac_outr hp_outl v ssa(hp) hp_outc v dda(3v3_hp) dcdc_stop dcdc_lx1 v ss12(dcdc) dcdc_lx2 dcdc_sw dcdc_in3v3 adc_mic_pga dcdc_downsel adc_mic_lna iic_sri_scl adc_mic_in sri_data_n v ssa(spdif) sri_data_p spdif_in sri_gchclk_n v dda(3v3_spdif) sri_gchclk_p v dda(3v3_adc) sri_fsync_n v dda(1v8_adc) sri_fsync_p adc_ref v dda (1v8_xtalh) adc_refn xtalh_in adc_refp xtalh_out adc_com v ssa(xtalh) v ssa(pll) v dde2 v dda(1v8_pll) v sse2 adc10b_gpa0 gpio_09/i2sin_2_ws v ddi2 gpio_05/uart_ncts v ssi2 gpio_04/uart_nrts gpio_03 i2sout_1_data gpio_02/mode_1 i2sout_2_data gpio_01/mode_0 adc10b_gpa1 adc10b_gpa2 adc10b_gpa3 v dda(3v3_adc10b) v ssa(adc10b) i2sout_bck v ssi3 v ddi3 gpio_08/i2sin_2_data gpio_07/uart_txs gpio_06/uart_rxs gpio_00 i2sout_ws 001aab020 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 56 55 54 53 52 51 15 16 17 18 19 61 60 59 58 57 26 27 28 29 30 31 32 33 34 35 36 37 38 39 45 46 47 48 49 50 10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 81 80 79 78 77 76 40 41 42 43 44 86 85 84 83 82
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 6 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 6.2 pin description table 2: pin description symbol pin special [1] type description digital supply voltage pins v ssi1 5 vssi core ground v ddi1 6 vddi core supply voltage v sse1 69 vsse3v3 core ground v dde1 70 vdde3v3 core supply voltage v sse2 88 vsse3v3 core ground v dde2 89 vdde3v3 core supply voltage v ddi2 45 vddco core supply voltage v ssi2 46 vssco core ground v ddi3 85 vddco core supply voltage v ssi3 86 vssco core ground dc-to-dc converter v usb(dcdc) 63 a vddco usb supply voltage (linear regulator) dcdc_out3v3 62 a vddco 3.3 v output voltage dcdc_lx1 61 a vddco coil connection for 3.3 v converter v ssi2(dcdc) 60 a vssco ground for switches 1.8 v and 3.3 v converter dcdc_lx2 59 a vddco coil connection for 1.8 v converter dcdc_sw 58 a vddco switch node dcdc_in3v3 57 a vddco 3.3 v input voltage dcdc_out1v8 56 a vddco 1.8 v output voltage v bat(dcdc) 55 a vddco battery supply voltage v ssa(dcdc) 54 a vssco ground double bonded clean and substrate dcdc_play 53 a apio play button signal dcdc_stop 52 a apio stop button signal dcdc_downsel 51 a apio one ore two battery selection crystal oscillator v ssa(xtalh) 90 vssco analog ground xtalh_out 91 apio 11.025 mhz clock output xtalh_in 92 apio 11.025 mhz clock input v dda(1v8_xtalh) 93 vddco analog supply voltage pll v dda(1v8_pll) 38 vddco analog supply voltage v ssa(pll) 37 vssco analog ground serial radio interface sri_fsync_p 94 a apio frame sync positive sri_fsync_n 95 a apio frame sync negative sri_gchclk_p 96 a apio gated channel clock positive
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 7 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband sri_gchclk_n 97 a apio gated channel clock negative sri_data_p 98 a apio data positive sri_data_n 99 a apio data negative serial radio interface i 2 c-bus iic_sri_scl 100 iic400kt5v clock input iic_sri_sda 1 iic400kt5v data input or output audio adc adc_com 36 a apio common mode reference voltage adc_refp 35 a apio positive reference voltage adc_refn 34 a apio negative reference voltage adc_ref 33 a apio reference voltage v dda(3v3_adc) 31 a vddco analog supply voltage (3.3 v) v dda(1v8_adc) 32 a vddco analog supply voltage (1.8 v) v ssa(adc) 22 a vssco analog ground adc_inr 23 a apio right input voltage adc_inl 24 a apio left input voltage adc_mic_pga 25 a apio pga input for ac coupling adc_mic_lna 26 a apio lna output for ac coupling adc_mic_in 27 a apio microphone input audio dac dac_refn 11 a apio negative reference voltage dac_refp 12 a apio positive reference voltage v dda(3v3_dac) 13 a vddco analog supply voltage dac_outl 14 a apio left line output voltage dac_outr 15 a apio right line output voltage headphone hp_com 21 a apio common mode reference voltage hp_outr 20 a apio right output voltage v dda(3v3_hp) 19 a vddco analog supply voltage hp_outc 18 a apio common output voltage v ssa(hp) 17 a vssco analog ground hp_outl 16 a apio left output voltage spdif v dda(3v3_spdif) 30 a vddco analog supply voltage spdif_in 29 a apio input voltage v ssa(spdif) 28 a vssco analog ground i 2 s-bus input i2sin_1_data 72 i iptht5v serial data channel 1 i2sin_1_ws 73 i/o bpts10tht5v word select channel 1 i2sin_1_bck 74 i/o bpts10tht5v bit clock channel 1 table 2: pin description continued symbol pin special [1] type description
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 8 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband gpio_10/i2sin_2_bck 7 i/o bpts10tht5v general purpose io/i 2 s-bus input bit clock channel 2 gpio_09/i2sin_2_ws 87 i/o bpts10tht5v general purpose io/i 2 s-bus input word select channel 1 gpio_08/i2sin_2_data 84 i/o bpts10tht5v general purpose io/i 2 s-bus input serial data channel 2 i 2 s-bus output i2sout_ws 76 i/o bpts10tht5v word select i2sout_bck 77 i/o bpts10tht5v bit clock i2sout_2_data 78 o ots10ct5v serial data channel 2 i2sout_1_data 79 o ots10ct5v serial data channel 1 control adc v ssa(adc10b) 44 a vssco analog ground v dda(3v3_adc10b) 43 a vddco analog supply voltage adc10b_gpa3 42 a apio analog general purpose input 3 adc10b_gpa2 41 a apio analog general purpose input 2 adc10b_gpa1 40 a apio analog general purpose input 1 adc10b_gpa0 39 a apio analog general purpose input 0 gpio gpio_13 10 i/o bpts10tht5v general purpose io gpio_12 9 i/o bpts10tht5v general purpose io gpio_11/sri_int 8 i/o general purpose io gpio_10/i2sin_2_bck 7 i/o bpts10tht5v general purpose io/i 2 s-bus input bit clock channel 2 gpio_09/i2sin_2_ws 87 i/o bpts10tht5v general purpose io/i 2 s-bus input word select channel 1 gpio_08/i2sin_2_data 84 i/o bpts10tht5v general purpose io/i 2 s-bus input serial data channel 2 gpio_07/uart_txs 83 i/o bpts10tht5v general purpose io gpio_06/uart_rxs 82 i/o bpts10tht5v general purpose io gpio_05/uart_ncts 81 i/o bpts10tht5v general purpose io gpio_04/uart_nrts 80 i/o bpts10tht5v general purpose io gpio_03 47 i/o bpts10tht5v general purpose io gpio_02/mode_1 48 i/o bpts10tht5v general purpose io/boot-up mode selection pin 1 gpio_01/mode_0 49 i/o bpts10tht5v general purpose io/boot-up mode selection pin 0 gpio_00 50 i/o bpts10tht5v general purpose io system i 2 c-bus iic_ms_scl 2 iic400kt5v clock input or output iic_ms_sda 3 iic400kt5v data input or output other clk_out2 75 o ots10ct5v clock output 2 table 2: pin description continued symbol pin special [1] type description
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 9 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband [1] a = analog. i = input. o = output. clk_out1 71 o ots10ct5v clock output 1 rstin_n 4 i ipthu5v system reset input jtag jtag_trst_n 68 i ipthdt5v reset input jtag_tck 67 i ipthdt5v clock input jtag_tdi 64 i ipthdt5v data input jtag_tms 65 i ipthdt5v mode select input jtag_tdo 66 o ots10ct5v data output table 3: cell types description cell name de?nition iptht5v input pad; push pull; ttl with hysteresis; 5 v tolerant ipthu5v input pad; push pull; ttl with hysteresis; pull-up; 5 v tolerant ipthdt5v input pad; push pull; ttl with hysteresis; pull-down; 5 v tolerant ots10ct5v output pad; 3-state; 10 ns slew rate control; 5 v tolerant bpts10tht5v bi-directional pad; plain input; 3-state output; 10 ns slew rate control; ttl with hysteresis; 5 v tolerant iic400kt5v i 2 c-bus pad; 400 khz i 2 c-bus speci?cation; 5 v tolerant apio analog pad; analog input/output vddi v dd pad connected to core v dd and internal v dd supply voltage rail in i/o ring vddco v dd pad connected to core v dd vdde3v3 v dd pad connected to external 3.3 v v dd supply voltage rail vssco v ss pad connected to core v ss vsse3v3 v ss pad connected to external 3.3 v v ss supply voltage rail vssi v ss pad connected to core v ss ; internal v ss supply voltage rail in i/o ring and substrate rail in i/o ring table 2: pin description continued symbol pin special [1] type description
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 10 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7. functional description 7.1 epics7b the epics7b core has only access to four of the ?ve memory spaces, pmem, xmem, ymem and dio. memory space io is only accessible via the dma. to distinguish between the memory spaces, 18-bit addressing is used, of which the two most signi?cant (ms) bits determine which space the address is in, see t ab le 4 . the epics7b only knows about the 16 least signi?cant bits and uses special instructions to access dio space. epics7b access: xmem is accessed by epics7b when using x in its instructions ymem is accessed by epics7b when using y in its instructions pmem is accessed by epics7b when it is fetching instructions dio is accessed by epics7b when using d in its instructions. all 18 bits are used when accessing memory via dma. the memory map of the system is described in t ab le 5 and figure 4 . [1] dsp control register bit 0 is selecting prom or biosrom. table 4: memory spaces two ms bits memory space 00 xmem 01 ymem 10 pmem 11 dio or io table 5: memory map address type words bits io 0x[3]ffff dsp control register 64 32 0x[3]fffe epics7b instruction register 32 0x[3]ffc0 to 0x[3]fffd user de?ned 64 32 dio 0x[3]ff00 to 0x[3]ff3f dio registers 24 pmem 0x[2]8000 to 0x[2]97ff pram 6144 0x[2]0000 to 0x[2]5fff prom [1] 24576 0x[2]0000 to 0x[2]00ff biosrom [1] ymem 0x[1]8000 to 0x[1]87ff yram 2048 0x[1]0000 to 0x[1]2fff yrom 12288 xmem 0x[0]ffc0 to 0x[0]ffff memory mapped registers 0x[0]0000 to 0x[0]2fff xram 12288
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 11 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband the control registers are split in two different spaces. one space is accessible only via dma while the other space is accessible both via dma and the dsp core. this space is therefore x-memory mapped. the location and de?nition of the control registers is described in t ab le 6 . fig 4. memory map 001aab383 dsp control register dio register epics instruction register user defined not used not used not used not used not used pram yram not used xram not used memory map yrom prom io and dio pmem ymem xmem prom or biosrom 0x [ 3 ] ffff 0x [ 2 ] ffff 0x [ 2 ] 7fff 0x [ 2 ] 9800 0x [ 1 ] ffff 0x [ 0 ] ffff 0x [ 0 ] 3000 0x [ 0 ] 0000 0x [ 0 ] 2fff 0x [ 0 ] ffc0 0x [ 0 ] ffbf 0x [ 1 ] 7fff 0x [ 1 ] 2fff 0x [ 1 ] 8800 0x [ 1 ] 87ff 0x [ 1 ] 8000 0x [ 1 ] 3000 0x [ 1 ] 0000 0x [ 2 ] 97ff 0x [ 2 ] 8000 0x [ 2 ] 6000 0x [ 2 ] 5fff 0x [ 2 ] 0100 0x [ 2 ] 00ff 0x [ 2 ] 0000 0x [ 3 ] fffe 0x [ 3 ] fffd 0x [ 3 ] ffc0 0x [ 3 ] ffbf 0x [ 3 ] ff40 0x [ 3 ] ff3f 0x [ 3 ] ff00 0x [ 3 ] feff 0x [ 3 ] 0000
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 12 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband the interrupts and connection order are described in t ab le 7 . table 6: control registers description register name address r/w description reset dsp pc 0x0 ffff w program counter register unde?ned sr1 0x0 fffe w status register 1 unde?ned sr2 0x0 fffd w status register 2 unde?ned rti_stack 0x0 fffc w interrupt stack register unde?ned io_dir 0x0 fffb w con?guration register 1 0x00 0000 io_mode 0x0 fffa w con?guration register 2 0x00 0ffd cr 0x3 ffff w control register i/o mapped 0x00 0000 eir 0x3 fffe w epics7b instruction register 0x00 0000 interrupt controller intc_pol 0x0 fff9 w polarity select 0x03 ffff intc_mode 0x0 fff8 w mode select 0x03 ffff intc_mask 0x0 fff7 w mask 0x03 ffff intc_status 0x0 fff6 r status unde?ned intc_test 0x0 fff5 w test 0x00 0001 intc_swclr 0x0 fff4 w software clear 0x00 0000 intc_slct 0x0 fff3 w user ?ag 0x00 0000 dma controller dmac_ic 0x0 fff2 r irq counter value 0x00 0000 table 7: interrupt ?ags interrupt ?ag symbol description 0 fi_dmac dmac interrupt 1 fi_sri_dma_rx_rdy sri rx dma block transfer interrupt 2 fi_flstart fsl start interrupt 3 fi_eventrouter event router interrupt 4 fi_sri_dma_tx_rdy sri tx dma block transfer interrupt 5 fi_i2sin_1 i 2 s-bus input 1 interrupt 6 fi_i2sin_2 i 2 s-bus input 2 interrupt 7 fi_spdif spdif input interrupt 8 fi_adc adc input interrupt 9 fi_dacall i 2 s-bus and dac outputs interrupt 10 fi_rsc_encrdy rsc encoder ready interrupt 11 fi_rsc_decrdy rsc decoder ready interrupt 12 fi_rsc_dmardy rsc dma block transfer ready interrupt 13 fi_vpb0 vpb0 interrupt 14 fi_vbp1 vpb1 interrupt 15 fi_uart uart interrupt 16 fi_i2c_dmardy i 2 c-bus m/s dma block transfer interrupt 17 fi_fslfast fsl fast interrupt
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 13 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband the outputs of the adc, i 2 s-bus inputs, spdif inputs and vpb buses are mapped to the inputs of the epics7b. the control of the dac, i 2 s-bus outputs and vpb buses are mapped to the outputs of the epics7b. table 8: dio input registers dio input register register name description 0 i2sin_1l i 2 s-bus input 1 left channel 1 i2sin_1r i 2 s-bus input 1 right channel 2 i2sin_2l i 2 s-bus input 2 left channel 3 i2sin_2r i 2 s-bus input 2 right channel 4 spdif l spdif input left channel 5 spdif r spdif input right channel 6 adc_l adc input left channel 7 adc_r adc input right channel 8 vpb0_di1 vpb0 data input 1 (bit 0 to bit 15) 9 vpb0_di2 vpb0 data input 2 (bit 16 to bit 31) 10 vpb1_di vpb1 data input (uart) 11 ts_counter 12 i2sin_1ts time stamp counter i2sin1 13 i2sin_2ts time stamp counter i2sin2 14 spdif_ts time stamp counter spdif 15 adc_ts time stamp counter adc 16 i2sout_ts time stamp counter i2sout 17 ts_counter table 9: dio output registers dio output register register name description 0 i2sout_1l i 2 s-bus output 1 left channel 1 i2sout_1r i 2 s-bus output 1 right channel 2 i2sout_2l i 2 s-bus output 2 left channel 3 i2sout_2r i 2 s-bus output 2 right channel 4 dac_l dac output left channel 5 dac_r dac output right channel 6 not connected 7 not connected 8 vpb0_do1 vpb0 data output 1 (bit 0 to bit 15) 9 vpb0_do2 vpb0 data output 2 (bit 16 to bit 31) 10 vpb0_addr vpb0 address 11 vpb1_do vpb1 data output (uart) 12 vpb1_addr vpb1 address 13 not connected 14 not connected
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 14 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.1.1 user registers the user registers are memory mapped control signals used to control integrated wireless audio baseband functionality. 15 not connected 16 not connected 17 not connected table 9: dio output registers continued dio output register register name description table 10: user register description register name address r/w description reset sri_tx_addr 0x0 ffde w serial radio interface dma from mem start address 0x000 0000 sri_tx_blksize 0x0 ffdd w serial radio interface dma from mem block size 0x000 0000 sri_mode 0x0 ffdc w serial radio interface mode control 0x000 0000 srim_tstart 0x0ffdb w serial radio interface master mode start time 0x000 0000 srim_tlink 0x0 ffda w serial radio interface master mode sync-link time 0x000 0000 srim_tidle 0x0 ffd9 w serial radio interface master mode idle time 0x000 0000 srim_dllen 0x0 ffd8 w serial radio interface master mode number downlink words 0x000 0000 srim_ullen 0x0 ffd7 w serial radio interface master mode number uplink words 0x000 0000 fsl_mode 0x0 ffd6 w frame sync lock mode control 0x000 0000 apll_control 0x0 ffd5 w audio pll direct control 0x000 0000 apll_select 0x0 ffd4 w audio pll direct control select 0x000 0000 spdif_status 0x0 ffd3 r spdif status 0x000 0000 fsy_inperiod 0x0 ffd2 r frame sync measured period 0x000 0000 fsy_refperiod 0x0 ffd1 r frame sync reference measured period 0x000 0000 fsy_phasedif 0x0 ffd0 r frame sync phase difference 0x000 0000 iwab_bootcfg 0x0 ffcf w SAA8200HL boot mode con?guration 0x000 0000 sri_status 0x0 ffce r serial radio interface status 0x000 0000 apll_ack 0x0 ffcd r audio pll direct control acknowledge 0x000 0000 rsc_status 0x0 ffcc r reed-solomon status 0x000 0000 rsc_control 0x0 ffcb w reed-solomon control 0x000 0000 rsc_addr 0x0 ffca w reed-solomon dma start address 0x000 0000 rsc_blksize 0x0 ffc9 w reed-solomon dma block size 0x000 0000
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 15 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.2 vpb0 bridge section 7.2 speci?es the interfaces and function of the vpb0 bridge. the vpb0 bridge acts as a bridge between a range of rtg ip blocks using the vpb bus and the epics7b dio interface. two bridges are used one to connect to several slow blocks and an additional one speci?cally for the uart. the vpb0 bridge forms the bridge between the epics7b and the clock generation unit, sri i 2 c-bus, watchdog timer, event router, i/o con?guration and the audio con?guration respectively. 7.2.1 vpb0 bridge address de?nitions sri_rx_addr 0x0ffc8 w serial radio interface dma to mem start address 0x000 0000 sri_rx_blksize 0x0ffc7 w serial radio interface dma to mem block size 0x000 0000 apll_m 0x0ffc6 w direct control of audio pll m value 0x000 0000 apll_n 0x0ffc5 w direct control of audio pll n value 0x000 0000 i2c_addr 0x0ffc4 w master/slave i 2 c-bus dma memory address 0x002 8000 i2c_blksize 0x0ffc3 w master/slave i 2 c-bus dma block size 0x000 0000 i2c_control 0x0ffc2 w master/slave i 2 c-bus control 0x000 0002 mpi_devaddr 0x0ffc1 w mpi device address 0x000 0048 table 10: user register description continued register name address r/w description reset table 11: vpb0 bridge interface description base address offset key description 0x0000 clock generation unit 0x0000 scr_lp0 switch control register for system pll clock 0x0004 scr_hp0 switch control register for audio pll clock 0x0008 scr_dcdc switch control register for dc-to-dc converter clock 0x000c scr_spdif switch control register for spdif clock 0x0010 scr_i2sin_1 switch control register for i2sin_1 bit clock 0x0014 scr_i2sin_2 switch control register for i2sin_2 bit clock 0x0018 scr_i2sout switch control register for i2sout bit clock 0x001c scr_sri_gchclk switch control register for sri gated channel clock 0x0020 scr_cr_clk_out1 switch control register for cr output 1 clock 0x0024 scr_cr_clk_out2 switch control register for cr output 2 clock 0x0028 scr_sri_chclk switch control register for sri reference channel clock 0x002c fs1_ lp0 frequency select side 1 for system pll clock 0x0030 fs1_ hp0 frequency select side 1 for audio pll clock 0x0034 fs1_ dcdc frequency select side 1 for dc-to-dc converter clock 0x0038 fs1_ spdif frequency select side 1 for spdif clock
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 16 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 0x003c fs1_ i2sin_1 frequency select side 1 for i2sin_1 bit clock 0x0040 fs1_ i2sin_2 frequency select side 1 for i2sin_2 bit clock 0x0044 fs1_ i2sout frequency select side 1 for i2sout bit clock 0x0048 fs1_ sri_gchclk frequency select side 1 for sri gated channel clock 0x004c fs1_ cr_clk_out1 frequency select side 1 for cr output 1 clock 0x0050 fs1_ cr_clk_out2 frequency select side 1 for cr output 2 clock 0x0054 fs1_ sri_chclk frequency select side 1 for sri reference channel clock 0x0058 fs2_ lp0 frequency select side 2 for system pll clock 0x005c fs2_ hp0 frequency select side 2 for audio pll clock 0x0060 fs2_ dcdc frequency select side 2 for dc-to-dc converter clock 0x0064 fs2_ spdif frequency select side 2 for spdif clock 0x0068 fs2_ i2sin_1 frequency select side 2 for i2sin_1 bit clock 0x006c fs2_ i2sin_2 frequency select side 2 for i2sin_2 bit clock 0x0070 fs2_ i2sout frequency select side 2 for i2sout bit clock 0x0074 fs2_ sri_gchclk frequency select side 2 for sri gated channel clock 0x0078 fs2_ cr_clk_out1 frequency select side 2 for cr output 1 clock 0x007c fs2_ cr_clk_out2 frequency select side 2 for cr output 2 clock 0x0080 fs2_ sri_chclk frequency select side 2 for sri reference channel clock 0x0084 ssr_ lp0 frequency select status for system pll clock 0x0088 ssr_ hp0 frequency select status for audio pll clock 0x008c ssr_ dcdc frequency select status for dc-to-dc converter clock 0x0090 ssr_ spdif frequency select status for spdif clock 0x0094 ssr_ i2sin_1 frequency select status for i2sin_1 bit clock 0x0098 ssr_ i2sin_2 frequency select status for i2sin_2 bit clock 0x009c ssr_ i2sout frequency select status for i2sout bit clock 0x00a0 ssr_ sri_gchclk frequency select status for sri gated channel clock 0x00a4 ssr_ cr_clk_out1 frequency select status for cr output 1 clock 0x00a8 ssr_ cr_clk_out2 frequency select status for cr output 2 clock 0x00ac ssr_ sri_chclk frequency select status for sri reference channel clock 0x00b0 pcr_spd_sysclk power control register for system clock 0x00b4 pcr_sysclk_div4 power control register for 0.25 f s system clock 0x00b8 pcr_uart_uclk power control register for uart clock 0x00bc pcr_vpb1_pclk power control register for vpb1 bus clock 0x00c0 pcr_uart_pclk power control register for uart bus clock 0x00c4 pcr_debounce_pclk power control register for debounce bus clock 0x00c8 pcr_cgu_pclk power control register for cgu bus clock 0x00cc pcr_wdog_pclk power control register for wdog bus clock 0x00d0 pcr_adc_pclk power control register for control adc bus clock 0x00d4 pcr_ioconf_pclk power control register for io con?guration bus clock 0x00d8 pcr_event_router_pclk power control register for event router bus clock 0x00dc pcr_sri_i2c_pclk power control register for sri i 2 c-bus clock table 11: vpb0 bridge interface description continued base address offset key description
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 17 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 0x00e0 pcr_adc_clk power control register for control adc system clock 0x00e4 pcr_i2c_ms_pclk power control register for m/s i 2 c-bus clock 0x00e8 pcr_rsc_pclk power control register for rsc bus clock 0x00ec pcr_extdmacntr_pclk power control register for external dma controller clock 0x00f0 pcr_dio2vpb0 _pclk power control register for dio2vpb0 bus clock 0x00f4 pcr_dio2vpb1_pclk power control register for dio2vpb1 bus clock 0x00f8 pcr_i2sin_1 _pclk power control register for i2sin_1 bus clock 0x00fc pcr_i2sin_2 _pclk power control register for i2sin_2 bus clock 0x0100 pcr_i2sout_1 _pclk power control register for i2sout_1 bus clock 0x0104 pcr_i2sout_2_pclk power control register for i2sout_2 bus clock 0x0108 pcr_adss _pclk power control register for adss bus clock 0x010c pcr_audio_config _pclk power control register for audio con?guration bus clock 0x0110 pcr_spdif _pclk power control register for spdif bus clock 0x0114 pcr_sri _pclk power control register for sri bus clock 0x0118 pcr_framesyncref power control register for sri frame sync reference 0x011c pcr_cr_i2sin_2_bck power control register for i2sin_2 bit clock 0x0120 pcr_cr_i2sin_1_bck power control register for i2sin_1 bit clock 0x0124 pcr_cr_i2sout_bck power control register for i2sout bit clock 0x0128 pcr_cr_i2sin_2_ws power control register for i2sin_2 word select 0x012c pcr_cr_i2sin_1_ws power control register for i2sin_1 word select 0x030 pcr_cr_i2sout_ws power control register for i2sout word select 0x0134 pcr_sdac_ns_clk power control register for sdac new sample 0x0138 pcr_sdac_dspclk power control register for sdac dsp clock 0x013c pcr_sadc_decclk power control register for sadc decimation ?lter clock 0x0140 pcr_sadc_sysclk power control register for sadc system clock 0x0144 pcr_dcdc_converter_clk power control register for dc-to-dc converter clock 0x0148 pcr_spdif_bck power control register for spdif bit clock from pad 0x014c pcr_i2sin_1_bck power control register for i2sin_1 bit clock from pad 0x0150 pcr_i2sin_2_bck power control register for i2sin_2 bit clock from pad 0x0154 pcr_i2sout_bck power control register for i2sout bit clock from pad 0x0158 pcr_sri_gcc_sho power control register for sri gated channel clock from pad 0x015c pcr_cr_clk_out1 power control register for crystal output 1 from pad 0x0160 pcr_cr_clk_out2 power control register for crystal output 2 from pad 0x0164 pcr_sri_chclk power control register for sri channel clock 0x0168 psr_spd_sysclk power status register for system clock 0x016c psr_sysclk_div4 power status register for 0.25 f s system clock 0x0170 psr_uart_uclk power status register for uart clock 0x0174 psr_vpb1_pclk power status register for vpb1 bus clock 0x0178 psr_uart_pclk power status register for uart bus clock 0x017c psr_debounce_pclk power status register for debounce bus clock 0x0180 psr_cgu_pclk power status register for cgu bus clock table 11: vpb0 bridge interface description continued base address offset key description
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 18 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 0x0184 psr_wdog_pclk power status register for wdog bus clock 0x0188 psr_adc_pclk power status register for control adc bus clock 0x018c psr_ioconf_pclk power status register for io con?guration bus clock 0x0190 psr_event_router_pclk power status register for event router bus clock 0x0194 psr_sri_i2c_pclk power status register for sri i 2 c-bus clock 0x0198 psr_adc_clk power status register for control adc system clock 0x019c psr_i2c_ms_pclk power status register for m/s i 2 c-bus clock 0x01a0 psr_rsc_pclk power status register for rsc bus clock 0x01a4 psr_extdmacntr_pclk power status register for external dma controller clock 0x01a8 psr_dio2vpb0 _pclk power status register for dio2vpb0 bus clock 0x01ac psr_dio2vpb1_pclk power status register for dio2vpb1 bus clock 0x01b0 psr_i2sin_1 _pclk power status register for i2sin_1 bus clock 0x01b4 psr_i2sin_2 _pclk power status register for i2sin_2 bus clock 0x01b8 psr_i2sout_1 _pclk power status register for i2sout_1 bus clock 0x01bc psr_i2sout_2_pclk power status register for i2sout_2 bus clock 0x01c0 psr_adss _pclk power status register for adss bus clock 0x01c4 psr_audio_config _pclk power status register for audio con?guration bus clock 0x01c8 psr_spdif _pclk power status register for spdif bus clock 0x01cc psr_sri _pclk power status register for sri bus clock 0x01d0 psr_framesyncref power status register for sri frame sync reference 0x01d4 psr_cr_i2sin_2_bck power status register for i2sin_2 bit clock 0x01d8 psr_cr_i2sin_1_bck power status register for i2sin_1 bit clock 0x01dc psr_cr_i2sout_bck power status register for i2sout bit clock 0x01e0 psr_cr_i2sin_2_ws power status register for i2sin_2 word select 0x01e4 psr_cr_i2sin_1_ws power status register for i2sin_1 word select 0x01e8 psr_cr_i2sout_ws power status register for i2sout word select 0x01ec psr_sdac_ns_clk power status register for sdac new sample 0x01f0 psr_sdac_dspclk power status register for sdac dsp clock 0x01f4 psr_sadc_decclk power status register for sadc decimation ?lter clock 0x01f8 psr_sadc_sysclk power status register for sadc system clock 0x01fc psr_dcdc_converter_clk power status register for dc-to-dc converter clock 0x0200 psr_spdif_bck power status register for spdif bit clock from pad 0x0204 psr_i2sin_1_bck power status register for i2sin_1 bit clock from pad 0x0208 psr_i2sin_2_bck power status register for i2sin_2 bit clock from pad 0x020c psr_i2sout_bck power status register for i2sout bit clock from pad 0x0210 psr_sri_gcc_sho power status register for sri gated channel clock from pad 0x0214 psr_cr_clk_out1 power status register for crystal output 1 from pad 0x0218 psr_cr_clk_out2 power status register for crystal output 2 from pad 0x021c psr_sri_chclk power status register for sri channel clock 0x0220 esr_spd_sysclk enable fraction divider for system clock 0x0224 esr_sysclk_div4 enable fraction divider for 0.25 f s system clock table 11: vpb0 bridge interface description continued base address offset key description
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 19 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 0x0228 esr_uart_uclk enable fraction divider for uart clock 0x022c esr_vpb1_pclk enable fraction divider for vpb1 bus clock 0x0230 esr_uart_pclk enable fraction divider for uart bus clock 0x0234 esr_debounce_pclk enable fraction divider for debounce bus clock 0x0238 esr_cgu_pclk enable fraction divider for cgu bus clock 0x023c esr_wdog_pclk enable fraction divider for wdog bus clock 0x0240 esr_adc_pclk enable fraction divider for control adc bus clock 0x0244 esr_ioconf_pclk enable fraction divider for io con?guration bus clock 0x0248 esr_event_router_pclk enable fraction divider for event router bus clock 0x024c esr_sri_i2c_pclk enable fraction divider for sri i 2 c-bus clock 0x0250 esr_adc_clk enable fraction divider for control adc system clock 0x0254 esr_i2c_ms_pclk enable fraction divider for m/s i 2 c-bus clock 0x0258 esr_rsc_pclk enable fraction divider for rsc bus clock 0x025c esr_extdmacntr_pclk enable fraction divider for external dma controller clock 0x0260 esr_dio2vpb0 _pclk enable fraction divider for dio2vpb0 bus clock 0x0264 esr_dio2vpb1_pclk enable fraction divider for dio2vpb1 bus clock 0x0268 esr_i2sin_1 _pclk enable fraction divider for i2sin_1 bus clock 0x026c esr_i2sin_2 _pclk enable fraction divider for i2sin_2 bus clock 0x0270 esr_i2sout_1 _pclk enable fraction divider for i2sout_1 bus clock 0x0274 esr_i2sout_2_pclk enable fraction divider for i2sout_2 bus clock 0x0278 esr_adss _pclk enable fraction divider for adss bus clock 0x027c esr_audio_config _pclk enable fraction divider for audio con?guration bus clock 0x0280 esr_spdif _pclk enable fraction divider for spdif bus clock 0x0284 esr_sri _pclk enable fraction divider for sri bus clock 0x0288 esr_framesyncref enable fraction divider for sri frame sync reference 0x028c esr_cr_i2sin_2_bck enable fraction divider for i2sin_2 bit clock 0x0290 esr_cr_i2sin_1_bck enable fraction divider for i2sin_1 bit clock 0x0294 esr_cr_i2sout_bck enable fraction divider for i2sout bit clock 0x0298 esr_cr_i2sin_2_ws enable fraction divider for i2sin_2 word select 0x029c esr_cr_i2sin_1_ws enable fraction divider for i2sin_1 word select 0x02a0 esr_cr_i2sout_ws enable fraction divider for i2sout word select 0x02a4 esr_sdac_ns_clk enable fraction divider for sdac new sample 0x02a8 esr_sdac_dspclk enable fraction divider for sdac dsp clock 0x02ac esr_sadc_decclk enable fraction divider for sadc decimation ?lter clock 0x02b0 esr_sadc_sysclk enable fraction divider for sadc system clock 0x02b4 esr_dcdc_converter_clk enable fraction divider for dc-to-dc converter clock esr_spdif_bck no fractional divider supported for this clock esr_i2sin_1_bck no fractional divider supported for this clock esr_i2sin_2_bck no fractional divider supported for this clock esr_i2sout_bck no fractional divider supported for this clock esr_sri_gcc_sho no fractional divider supported for this clock table 11: vpb0 bridge interface description continued base address offset key description
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 20 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 0x02b8 esr_cr_clk_out1 enable fraction divider for crystal output 1 from pad 0x02bc esr_cr_clk_out2 enable fraction divider for crystal output 2 from pad 0x02c0 esr_sri_chclk enable fraction divider for sri channel clock 0x02c4 bcr_lp0 base control register for system pll clock 0x02c8 bcr_hp0 base control register for audio pll clock 0x2cc fdc_spd_sysclk fractional divider control for system clock 0x2d0 fdc_sysclk_div4 fractional divider control for 0.25 f s system clock 0x02d4 fdc_uart_uclk fractional divider control for uart clock 0x02d8 fdc_debounce_pclk fractional divider control for debounce bus clock 0x02dc fdc_adc_clk fractional divider control for control adc system clock 0x02e0 fdc_dio_pclk fractional divider control for dio interface clock 0x02e4 fdc_audio_pclk fractional divider control for audio bus clock 0x02e8 fdc_framesyncref fractional divider control for sri frame sync reference 0x02ec fdc_cr_i2sin_2_bck fractional divider control for i2sin_2 bit clock 0x02f0 fdc_cr_i2sin_1_bck fractional divider control for i2sin_1 bit clock 0x2f4 fdc_cr_i2sout_bck fractional divider control for i2sout bit clock 0x02f8 fdc_i2s_ws fractional divider control for i2s word select 0x02fc fdc_sdac_ns_clk fractional divider control for sdac new sample 0x300 fdc_audio_sysclk fractional divider control for audio system clock 0x0304 fdc_dcdc_converter_clk fractional divider control for dc-to-dc converter clock 0x0308 fdc_cr_clk_out1 fractional divider control for crystal output 1 from pad 0x030c fdc_cr_clk_out2 fractional divider control for crystal output 2 from pad 0x0310 fdc_sri_chclk fractional divider control for sri channel clock 0x0c00 cnf_powermode power-down cgu 0x0c04 cnf_wd_bark watchdog bark register 0x0c08 reserved 0xc0c reserved 0x0c10 osc_on activate crystal oscillator 0x0c14 osc_bypass bypass crystal oscillator 0x0c18 cnf_uart_rst_n reset for uart 0x0c1c cnf_i2sin_1_rst_n reset for i2s input 1 0x0c20 cnf_i2sin_2_rst_n reset for i2s input 2 0x0c24 cnf_i2sout_1_rst_n reset for i2s output 1 0x0c28 cnf_i2sout_2_rst_n reset for i2s output 2 0x0c2c cnf_dec_rst_n reset for decimation ?lter 0x0c30 cnf_int_rst_n reset for interpolation ?lter 0x0c34 cnf_spdif_rst_n reset for spdif 0xc38 cnf_epics7b_rst_n reset for epics7b 0x0c3c cnf_dio2vpb0_rst_n reset for vpb0 bridge 0x0c40 cnf_dio2vpb1_rst_n reset for uart vpb bridge 0x0c44 cnf_ms_i2c_rst_n reset for m/s i 2 c-bus table 11: vpb0 bridge interface description continued base address offset key description
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 21 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 0x0c48 cnf_sri _rst_n reset for serial radio interface 0x0c4c cnf_rsc_rst_n reset for reed-solomon codec 0x0c50 cnf_sri_i2c_rst_n reset for sri i 2 c-bus 0x0c54 cnf_ad10bit_rst_n reset for control adc 0x0c58 cnf_fsl_rst_n reset for frame sync lock 0x0c5c cnf_gcc_rst_n reset for gated channel clock 0x0c60 cnf_ad10bit_prst_n preset for control adc 0x0c64 hp0_fin_select audio clock pll input select 0x0c68 hp0_mdec audio clock pll m divider 0x0c6c hp0_ndec audio clock pll n divider 0x0c70 hp0_pdec audio clock pll p divider 0x0c74 hp0_mode audio clock pll mode 0x0c78 hp0_status audio clock pll status 0x0c7c hp0_ack audio clock pll acknowledge 0x0c80 hp0_req audio clock pll change request 0x0c84 hp0_inselr audio clock pll input bandwidth selection 0x0c88 hp0_inseli audio clock pll input bandwidth selection 0x0c8c hp0_inselp audio clock pll input bandwidth selection 0x0c90 hp0_selr audio clock pll input bandwidth selection 0x0c94 hp0_seli audio clock pll input bandwidth selection 0x0c98 hp0_selp audio clock pll input bandwidth selection 0x0c9c lp0_fin_select system clock pll input select 0x0ca0 lp0_pwd system clock pll power-down 0x0ca4 lp0_bypass system clock pll bypass 0x0ca8 lp0_lock system clock pll in-lock 0x0cac lp0_direct system clock pll direct cco control 0x0cb0 lp0_msel system clock pll m divider 0x0cb4 lp0_psel system clock pll p divider 0x1000 sri i 2 c-bus 0x0000 rx receive fifo 0x0000 tx transmit fifo 0x0004 sts status register 0x0008 ctl control register 0x000c clkhi clock divisor high 0x0010 clklo clock divisor low 0x0014 addr i 2 c-bus address 0x0028 txs slave transmit fifo 0x2000 control adc 0x0000 adc_r0 adc data channel 0 0x0004 adc_r1 adc data channel 1 0x0008 adc_r2 adc data channel 2 table 11: vpb0 bridge interface description continued base address offset key description
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 22 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 0x000c adc_r3 adc data channel 3 0x0010 adc_r4 adc data channel 4 0x0014 adc_r5 adc data channel 5 0x0018 adc_r6 adc data channel 6 0x001c adc_r7 adc data channel 7 0x0020 adc_con control register 0x0024 adc_csel_res channel and resolution selection register 0x0028 adc_int_enable interrupt enable register 0x002c adc_int_status interrupt status register 0x0030 adc_int_clear interrupt clear register 0x3000 watchdog timer 0x0000 ir interrupt register 0x0004 tcr_reg timer control register 0x0008 tc timer counter 0x000c pr_reg pre-scale register 0x0010 pc pre-scale counter 0x0014 mcr match control register 0x0018 mr0 match register 0 0x001c mr1 match register 1 0x003c emr external match register 0x4000 event router 0x0804 dtr_gp_13_irq de-bounce time register for gp_13_irq 0x0808 dtr_gp_12_irq de-bounce time register for gp_12_irq 0x080c dtr_gp_11_irq de-bounce time register for gp_11_irq 0x0810 dtr_gp_10_irq de-bounce time register for gp_10_irq 0x0814 dtr_gp_9_irq de-bounce time register for gp_9_irq 0x0818 dtr_gp_8_irq de-bounce time register for gp_8_irq 0x081c dtr_gp_7_irq de-bounce time register for gp_7_irq 0x0820 dtr_gp_6_irq de-bounce time register for gp_6_irq 0x0824 dtr_gp_5_irq de-bounce time register for gp_5_irq 0x0828 dtr_gp_4_irq de-bounce time register for gp_4_irq 0x082c dtr_gp_3_irq de-bounce time register for gp_3_irq 0x0830 dtr_gp_2_irq de-bounce time register for gp_2_irq 0x0834 dtr_gp_1_irq de-bounce time register for gp_1_irq 0x0838 dtr_gp_0_irq de-bounce time register for gp_0_irq 0x0c00 pend input event pending status 0x0c20 int_clr interrupt clear 0x0c40 int_set interrupt set 0x6000 input/output con?guration 0x0000 ioc_pins read pin values 0x0010 ioc_mode0 load mode 0 table 11: vpb0 bridge interface description continued base address offset key description
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 23 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.3 clock generation unit the clock generation unit (cgu) generates all clock signals required for the SAA8200HL, it contains: ? a crystal oscillator ? for low power mode the internal dc-to-dc converter clock can be used as system clock ? an audio pll to generate audio sample frequencies ? a system pll to generate the clocks for the vpb bus and the dsp subsystem ? a clock switch block ? a con?guration register block ? a reset and power block. an 11.2896 mhz oscillator or an external 11.025 mhz clock (provided by the tea7000) can be used in combination with the two plls and the external clocks to generate the system frequencies. all plls are programmed with the registers in the register con?guration block. 0x0014 ioc_mode0_set set mode 0 0x0018 ioc_mode0_reset reset mode 0 0x0020 ioc_mode1 load mode 1 0x0024 ioc_mode1_set set mode 1 0x0028 ioc_mode1_reset reset mode 1 0x7000 audio con?guration 0x0000 i2s_format_settings i 2 s-bus format settings 0x0004 i2s_mux_settings i 2 s-bus multiplexer settings 0x0008 spdif_status spdif status 0x000c spdif_irq_en spdif interrupt enable 0x0010 spdif_irq_status spdif interrupt status 0x0014 spdif_irq_clear spdif interrupt clear 0x0018 sdac_ctrl_inti audio dac input interpolation ?lter control 0x001c sdac_ctrl_into audio dac output interpolation ?lter control 0x0020 sdac_settings audio dac control 0x0024 sadc_ctrl_sdc audio adc ampli?ers control 0x0028 sadc_ctrl_adc audio adc control 0x002c sadc_ctrl_deci audio adc input decimation ?lter control 0x0030 sadc_ctrl_deco audio adc output decimation ?lter control 0x0034 e7b_irq epics7b interrupt request 0x0038 pd_adc10b power-down control adc 0x003c set_dcdc1v8_adjust dc-to-dc converter adjust output voltage (1.8 v) 0x0040 set_dcdc3v3_adjust dc-to-dc converter adjust output voltage (3.3 v) 0x0044 dcdc_clockstable dc-to-dc converter clock stable signal table 11: vpb0 bridge interface description continued base address offset key description
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 24 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.3.1 crystal oscillator the crystal oscillator is a 50 mhz pierce crystal oscillator with amplitude control. it can be used in many applications e.g. as a digital reference for digital circuits, a/d and d/a clocking, etc. it is a robust design and can be used across a large frequency range. features: ? on-chip biasing resistance ? amplitude controlled ? large frequency range: 1 mhz to 20 mhz ? slave mode ? power-down mode ? bypass test mode. 7.3.2 audio pll the audio pll is a multi purpose pll. features: ? integrated pll with on-chip current controlled oscillator (cco), no external components for clock generation ? input frequency range: 100 khz to 150 mhz ? cco output frequency: 275 mhz to 550 mhz ? output frequency range: 4.3 mhz to 550 mhz ? programmable pre-divider, feedback-divider and post-divider ? on the ?y adjustment of the clock possible ? positive edge locking ? frequency limiter to avoid hang-up of the pll ? lock detector ? power-down mode ? possibility to bypass whole pll, the post-divider or the pre-divider ? possibility to disable the output clock ? skew mode ? free running mode ? scan mode ? maximum peak cycle-to-cycle output jitter = 200 ps.
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 25 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.3.3 system pll the dsp-pll works in normal operating mode with feedback-divider and with post-divider, this means that the base for the clock signal is the current controlled oscillator (f out = f cco/p ), running on 264.6 mhz. the output clock (f out ) is divided-by-2 to generate a 132.3 mhz clock. features: ? integrated pll with on-chip current controlled oscillator (cco), no external components for clock generation ? functional down to 1.2 v (with reduced frequency range) ? 10 mhz to 25 mhz input frequency range ? 9.75 mhz to 160 mhz selectable output frequency with 50 % output duty cycle ? 156 mhz to 320 mhz cco frequency range ? power-down mode ? input clock bypass mode ? lock detector available ? current consumption maximum 1 ma ? maximum peak cycle-to-cycle output jitter = 300 ps. 7.4 serial radio interface features: ? interface between wireless audio baseband processor and wireless audio radio ic ? bi-directional 3-wire serial interface ? can be locked to audio sample frequencies ? enables end-to-end audio clock synchronization ? supports master and slave modes ? supports continuous and high speed repetitive burst mode ? control of the radio ic is handled via a separate i 2 c-bus interface ? designed for minimal interference with the radio chip. 7.5 sri i 2 c-bus the i 2 c-bus master/slave module provides a serial interface that meets the i 2 c-bus speci?cation and supports all transfer modes from and to the i 2 c-bus. it supports the following functionality: ? it supports both the normal mode (100 khz scl) and the fast mode (400 khz scl) ? it has word (32-bit) access from the cpu side ? interrupt generation on received or sent byte (and some special cases). the purpose of the sri i 2 c-bus is to allow the download of program code from an external eeprom at start-up, con?guration and monitoring of the radio ic (tea7000), and storage/retrieval of application speci?c parameters in an external data eeprom.
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 26 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.6 system i 2 c-bus interface a master and slave dma interface to the epics7b sub-system and the means to select one or the other are provided. the i 2 c-bus master/slave module provides a serial interface that meets the i 2 c-bus speci?cation and supports all transfer modes from and to the i 2 c-bus. features: ? supports both the normal mode (100 khz scl) and the fast mode (400 khz scl) ? 32-bit word access from the cpu side ? interrupt generation on received or sent byte (and some special cases) ? four modes of operation: C master transmitter C master receiver C slave transmitter C slave receiver. 7.7 control adc this section describes the multi-channel 10-bit control adc interface module, a module that connects an adc to a dsp. the adc interface module can be used for observing battery voltage. the interface can be divided into two main modules; a 10-bit adc and an adc controller. the 10-bit adc is a 10-bit successive approximation adc. the adc controller module is responsible for the communication between the adc and dsp. features: ? four analog input channels, selected by an analog multiplexer ? programmable adc resolution from 2-bit to 10-bit ? single adc scan mode and continuous adc scan mode ? converted digital values are stored in a 2 10-bit register ? power-down mode. 7.8 watchdog timer once the watchdog is enabled, it will monitor the programmed time out period and generates a reset request when the period expires. in normal operation the watchdog is triggered periodically, resetting the watchdog counter and ensuring that no reset is generated. in the event of a software or hardware failure preventing the cpu from triggering the watchdog, the time out will be exceeded and a reset requested from the cgu. the interrupt pin of this watchdog timer is not connected to the interrupt controller. instead of this, two pins m0 and m1 are used which will generate events. pins m0 and m1 will generate events when their match register matches the timer counter (tc) register.
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 27 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband the watchdog timer in the SAA8200HL can be used as follows: ? as watchdog, the m1 output is used for generating an event to the cgu, which requests a reset. ? as timer, the m0 output is used for generating an event to the event router, which generates an interrupt to the interrupt controller. ? as watchdog and as timer, the value of the mcr0 has to be lower than the value of mcr1 (otherwise unwanted resets could be generated by the cgu). 7.9 reed-solomon codec the reed-solomon codec is an essential part of the baseband ic. it allows redundancy to be added to the transmitted bits so that transmission errors can be corrected at the receiving end. the reed-solomon codec will provide some ?exibility to the customer to choose packet length. for sbc based applications the reed-solomon block length will be such that it contains one or two sbc-encoded audio frames. the reed-solomon codec is a hardware block that makes use of a locally attached memory for i/o, work space and temporary storage. the communication between this local ram and the epics7b x-memory space will happen via the external dma controller. features: ? 8-bit; 1-byte symbols ? 256-byte blocks ? 16 parity bytes ? no interleaving (for latency reduction) ? automatic zero insertion (virtual zero padding). 7.10 event router this module can be used in low power systems to request power-up or start a clock on an external or internal event. it can also be used to generate interrupts as a result: ? provides bus-controlled routing of input events to multiple outputs for use as interrupts or wake-up signals ? input events can be used either directly or latched (edge detected) as an interrupt source: C direct interrupts will disappear when the event becomes inactive C latched interrupts will remain active until they are explicitly cleared. ? interrupt events can be inverted (programmable) ? each interrupt can be masked on event level ? interrupt event detect status can be read per interrupt type ? interrupt detection is fully asynchronous (no active clock required). the event router provides bus control over the interrupt system. the event sources can be de?ned, their polarity and activation type selected, also each input can be routed to any output(s) at reset.
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 28 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband table 12: event router connections overview event name description input 0 spdif_in 1 gp_13_irq interrupt from general purpose pin 2 gp_12_irq interrupt from general purpose pin 3 gp_11_irq interrupt from general purpose pin 4 gp_10_irq interrupt from general purpose pin 5 gp_9_irq interrupt from general purpose pin 6 gp_8_irq interrupt from general purpose pin 7 gp_7_irq interrupt from general purpose pin 8 gp_6_irq interrupt from general purpose pin 9 gp_5_irq interrupt from general purpose pin 10 gp_4_irq interrupt from general purpose pin 11 gp_3_irq interrupt from general purpose pin 12 gp_2_irq interrupt from general purpose pin 13 gp_1_irq interrupt from general purpose pin 14 gp_0_irq interrupt from general purpose pin 15 i2c_sri_nintr i 2 c-bus sri event interrupt 16 adc10b_irq control adc event interrupt 17 fsl_start_irq framesynclock (fsl) start of frame 18 fsl_fast_irq framesynclock (fsl) fast interrupt for apll control 19 xdma_i2c_dmardy block transfer i 2 c-bus ms ready 20 xdma_mpiardy block transfer i 2 c-bus mpi ready 21 sri_txfifo_emptylevel sri txfifo reached empty level 22 sri_rxfifo_fulllevel sri rxfifo reached full level 23 sri_txfifo_underrun exception: txfifo underrun occurred 24 sri_rxfifo_overrun exception: rxfifo overrun occurred 25 wdt_nint watchdog timer event interrupt 26 wdt_m0 watchdog time match 0 27 wdt_m1 watchdog time match 1 28 sri_uld_req sri output 0 cascaded_interrupt_0 epics7b interrupt 1 watchdog_cap0_int 2 cgu_wakeup cgu wake-up interrupt
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 29 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.11 spdif inputs one input is provided, this spdif input is fed through a bit slicer which is used to re-generate the bitstream signal, allowing for a higher robustness of the link. the spdif input hardware consists of a series connection of a bit slicer, which is an analog module, the spdif decoder and a spdif input block. this spdif input block is almost the same as the spdif input blocks which are connected to the spdif input pads. the only difference between the spdif input blocks is that the input format of the spdif input block is ?xed in hardware to accept only spd3 format. the spdif decoder is running on a dedicated clock, which should lie between 36 mhz and 69 mhz. in this clock domain signal spd3_bck is generated, which is treated by the i 2 s-bus input block as a bit clock. this bit clock is again routed via the cgu to be able to insert the test clock during test mode. the spdif input decoder latches its output data on the negative edge of spd3_bck. the i 2 s-bus input will latch the data on the positive edge of the bit clock. this guarantees reliable data transfer even though the clock is delayed by the path through the cgu. the word select from the spdif input decoder is routed to the cgu. this makes it possible to lock the audio pll to the incoming spdif stream. 7.12 i 2 s-bus the supported audio formats for the control modes are: ? i 2 s-bus ? lsb-justi?ed, 16-bit ? lsb-justi?ed, 18-bit ? lsb-justi?ed, 20-bit ? lsb-justi?ed, 24-bit (only for the output interface). the bit clock bck can be up to 128f s , or in other words the bck frequency is 128 times the ws frequency or less: f bck 128f ws .
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 30 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband the ws edge must coincide with the negative edge of the bck at all times for proper operation of the digital i/o data interface . fig 5. serial interface input and output formats 16 msb b2 b3 b4 b5 b6 left lsb-justified format 20-bit ws bck data right 15 18 17 20 19 2 1 b19 lsb 16 msb b2 b3 b4 b5 b6 15 18 17 20 19 2 1 b19 lsb msb msb b2 2 1 > = 8 12 3 left i 2 s-bus format ws bck data right 3 > = 8 msb b2 001aab453 16 b5 b6 b7 b8 b9 b10 left lsb-justified format 24-bit ws bck data right 15 18 17 20 19 22 21 23 24 2 1 b3 b4 msb b2 b23 lsb 16 b5 b6 b7 b8 b9 b10 15 18 17 20 19 22 21 23 24 21 b3 b4 msb b2 b23 lsb 16 msb b2 left lsb-justified format 16-bit ws bck data right 15 2 1 b15 lsb 16 msb b2 15 2 1 b15 lsb 16 msb b2 b3 b4 left lsb-justified format 18-bit ws bck data right 15 18 17 2 1 msb b2 b3 b4 b17 lsb 16 15 18 17 2 1 b17 lsb
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 31 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.12.1 i 2 s-bus inputs two i 2 s-bus inputs are provided, one of the two has dedicated pins, the second is multiplexed using pin gpio8 to gpio10. the i 2 s-bus inputs can be used in slave and master mode. in slave mode an external i 2 s-bus source generates the bit clock and in master mode the SAA8200HL generates the bit clock. in slave mode the bit clock arrives on pad i2sin_x_bck and is led to the cgu input xt_i2sin_x_bck. this input should be switched directly to the cgu output i2sin_x_bck which delivers the bit clock for the i 2 s-bus blocks. in slave mode the audio pll needs to lock on the incoming source. this can best be done on the bit clock or on the word select. the bit clock is the preferred source because of its higher frequency. the audio pll has problems with locking on frequencies below 100 khz. if the ratio between the bit clock and the sample frequency is not known, the source word select can be used. the digital audio source will put out the data and the word select on the negative edge of the bit clock and these will be sampled by the i 2 s-bus block on the positive edge of the bit clock. 7.12.2 i 2 s-bus outputs two i 2 s-bus outputs are provided, both have dedicated data pins but the word select and bit clock for both outputs are shared. depending on the application the source of the audio pll could have an other input, then the fractional dividers should be programmed to account for the difference in clock frequency. the i2s_out can only be used in master mode. for this reason the output enable of the i2s_out_ws and i2s_out_bck pads is always active in functional mode. the bit clock generated by the cgu is inverted with respect to the word select, such that word select changes on a negative edge of the bit clock. 7.13 time stamp counters a time stamp counter has been included to allow the software to get an indication of the audio clocks. the time stamp counter output is hardwired to seven epics7b input registers. each input register will be latched by another strobe signal. these strobe signals are generated by the audio interfaces i2sin, spdif, adc, i2sout and dac. this way each sample of each audio source and sink can be labeled with a time stamp. the time stamp increases by one every dsp clock tick, and will wrap-round at value (2 24 - 1).
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 32 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.14 dma controller the purpose of the external dma controller block is to share the external dma channel of the epics7b dsp sub system between a number of external peripherals: the serial radio interface, the reed-solomon codec, the i 2 c-bus m/s and mpi. the controller needs to arbitrate between those blocks. features: ? interface between external dma hardware blocks and the epics7b dsp subsystem ? allows hardware blocks to read/write directly to x-, y-, p-memory and to internal dsp registers. ? supports single word memory access and memory block transfers of programmable length. ? signals block transfer ready per requesting hardware device ? arbiter priority schedule between four requesting sources (sri, i 2 c-bus m/s, rsc and mpi). ? each requesting hardware block has its own start address and block transfer size register ? dispatches acknowledges and keeps track of progress of each block transfer ? signals block transfer ready per requesting hardware device. 7.15 i/o con?guration the input/output con?guration (ioconf) is designed to provide developers a set of registers. this can be used for con?guration of various on chip components especially a pad multiplexer. the ioconf block is used to provide individual control and visibility for a set of pads. in conjunction with a set of pad multiplexers, individual pads can be switched either in normal operation mode, or in gpio mode. in gpio mode, a pad is fully controllable. through the ioconf, individual pad levels can be observed in both normal and gpio modes. functional pads can be grouped into function blocks. all output values in a function block can be set simultaneously by accessing a single register. changing modes for all pads within a function block requires at most two register access. all input values in a function block can be read simultaneously by accessing a single register. input values are not registered and always read directly from the pads input driver regardless of the mode of the pad. for each function block there are two registers holding the control mode. mode bit 1 leaves the ioconf inverted as it is intended to be used as inverted (output-) enable. each register can be written and read, has con?gurable pad names per bit (maximum 32) and provides set and clear access methods (set/clear bit when 1), and con?gurable reset value. con?gurable pad names are provided in order to enhance readability and consistency of both hdl and generated c header ?le.
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 33 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.16 vpb1 bridge this section describes the interfaces and function of the vpb1 bridge. the vpb1 bridge acts as a bridge between the uart and the epics7b dio interface. two bridges are used; one to connect to several slow blocks and an additional one speci?cally for the universal synchronous receiver transmitter, which is commonly used to implement a serial interface. in any case where a device needs a low overhead, standard, low performance interface, a uart can be used. the uart includes advanced features like a fractional clock divider. 7.17 uart con?guration the uart interface is used to be implemented as a serial interface to, for example a modem and is compatible with the industry standards 16650 uarts. no full modem interface is included, only the cts and rts modem signals are available. the uart interface can also be con?gured as an irda (infrared digital association) sir (serial infrared) interface, which has a pulse and polarity compliancy with the irda version 1.0 physical layer speci?cation. table 13: mode settings mode[1:0] pin multiplexer mode 00 gpio; high-impedance 01 normal operation; controlled by subsystem 10 gpio drive low 11 gpio drive high table 14: vpb1 bridge interface description base address offset key description 0x0000 uart 0x0000 uart_rbr receive fifo 0x0000 uart_thr transmit fifo 0x0004 uart_ier interrupt enable register 0x0008 uart_iir interrupt id register 0x0008 uart_fcr fifo control register 0x000c uart_lcr line control register 0x0010 uart_mcr modem control register 0x0014 uart_lsr line status register 0x0018 uart_msr modem status register 0x001c uart_scr scratch pad register 0x0000 uart_dll divisor latch lsb 0x0004 uart_dlm divisor latch msb 0x0028 uart_fdr fractional divider register
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 34 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.18 audio con?guration the audio con?guration block gives access to the following system settings: ? i 2 s-bus input/output format settings ? status of spdif module ? spdif interrupt request ? sdac control and status registers ? sadc control and status registers ? interrupt request to epics7b; with automatically clearing register ? power-down of the multi-channel 10-bit control adc ? dc-to-dc converter output voltage settings ? dc-to-dc clock-stable indicator. 7.19 audio input 7.19.1 adc analog front-end the analog front-end of the adc consists of one stereo adc with a selector in front of it. using this selector one can either select the microphone input with the microphone ampli?er (lna) with a ?xed 30 db gain or the line input. the microphone input as well as the line inputs have a programmable gain ampli?er (pga) that allows gain control from 0 db to 24 db in steps of 3 db. the input impedance of the pga (line in) is 12 k w , for the lna this is 5 k w . 7.19.1.1 applications and power-down modes the following power-down and functional modes are supported: ? power-down mode in which the current consumption is very low (only leakage currents). in this mode there is no reference voltage at the line input. ? line-in mode, in which the pga can be used. ? microphone mode in which the rest of the non-used pgas and adcs are powered down. in this mode the mono microphone signal can be sent to both left and right input of the decimation ?lter. this is done with a separate multiplexer in front of the decimation input. this multiplexer is controlled by bit sel_mic in the i 2 c-bus control interface. ? mixed pga and lna mode with one line-in and one microphone input. fig 6. analog front-end 001aab455 mic left right left_out right_out adc adc sdc pga sdc pga sdc pga lna
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 35 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.19.1.2 lna lna, a low noise microphone ampli?er with nominal gain of 30 db. 7.19.1.3 pga the input signal is ampli?ed with a gain set by control bits ctrl[3:0]. the resulting signal will be available at v out . if control bit ctrl 3 = 1 the gain is set to 24 db independent of the other bits. if ctrl3 = 0 the gain is set for other (lower) settings. the pga is based on an inverting ampli?er architecture. the feedback resistance exists of a resistor string. by switching between different resistors with the use of a 4-bit digital decoder the gain of the ampli?er can be modi?ed. the gain can be set in steps of 3 db from 0 db up to 24 db (see t ab le 15 ). the pga is designed to handle a nominal 1 v (rms) input level. a systematic gain of - 1.94 db is added to accommodate the 800 mv (rms) input level of a single-to-differential converter that is normally connected to the pga output. the power-down signal is controlled by the digital core of the SAA8200HL. 7.19.1.4 applications with 2 v (rms) input for the line-in mode it is preferable to have 0 db and 6 db gain setting in order to be able to apply both 1 v (rms) and 2 v (rms) (using series resistance). for this purpose a pga is used which has 0 db to 24 db gain with 3 db steps. in applications in which a 2 v (rms) input signal is used, a 12 k w resistor must be used in series with the input of the adc. this forms a voltage divider together with the internal adc resistor and ensures that only 1 v (rms) maximum is input to the SAA8200HL. using this application for a 2 v (rms) input signal, the switch must be set to 0 db. when a 1 v (rms) input signal is input to the adc in the same application, the gain switch must be set to 6 db. table 15: pga gain settings ctrl3 ctrl2 ctrl1 ctrl0 gain 00000 db 00013 db 00106 db 00119 db 010012 db 010115 db 011018 db 011121 db 1 x x x 24 db input signal is 2 v (rms); v dd = 3 v. fig 7. adc front-end with pga (line-in input) 001aab456 12 k w 12 k w pga input signal external resistor
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 36 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband an overview of the maximum input voltages allowed against the presence of an external resistor and the setting of the gain switch is given in t ab le 16 ; the power supply voltage is assumed to be 3 v. 7.19.1.5 sdc the single-to-differential converter (sdc) consists of an inverting ampli?er and a ?lter network. the input is dc coupled, which means that decoupling must be done in front of this module in case the input signal has a different common mode level than the sdc. for optional biasing conditions, the sdc requires a sourcing bias current (into an nmos transistor) that is preferably proportional to the analog supply voltage. 7.19.2 decimation ?lter (adc) the decimation from 128fs is performed in two stages (see figure 8 ). the ?rst stage realizes sin(x)/x characteristics with decimation factor of 16. the second stage consists of three half-band ?lters, each decimating by a factor of 2. the ?lter characteristics are shown in t ab le 17 . table 16: application modes using input gain stage resistor 12 k w input gain switch maximum input voltage present 0 db 2 v (rms) present 6 db 1 v (rms) absent 0 db 1 v (rms) absent 6 db 0.5 v (rms) table 17: filter characteristics description conditions value unit decimation ?lter pass band ripple up to 0.45f s 0.02 db stop band from 0.55f s - 60 db overall gain dc 3 db dynamic range up to 0.45f s 140 db droop at 0.45f s - 0.18 db dc blocking ?lter 1 pass band ripple none db pass band gain 0 db droop at 0.00045f s 0.5 db dc attenuation > 40 db dynamic range up to 0.45f s > 110 db dc blocking ?lter 2 pass band ripple none db pass band gain 0 db droop at 0.00045f s 0.031 db dc attenuation > 40 db dynamic range up to 0.45f s > 110 db
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 37 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.19.2.1 volume control the decimator is equipped with a digital volume control. this volume control is separate for left and right and can be set via the sadc_ctrl_deci register. the range is from +24 db down to - 63 db and mute in steps of 0.5 db. 7.19.2.2 dc blocking ?lter two optional 1st order in?nite impulse response (iir) high-pass ?lters are provided to remove unwanted dc components from the input (dc offset, dc dither) and/or volume control output to avoid clipping when using large gain settings. these ?lters may be bypassed by setting bits en_dcfilti (sadc_ctrl_deci[20]) and/or en_dcfilto (sadc_ctrl_deci[19]) to a logic 0, which is necessary when fast settling of the decimator is required. on recovery from power-down or after a reset, the parallel output data on bits dout_l[23:0] and dout_r[23:0] is held at logic 0 until valid data is available from the decimation ?lter. this time depends on which of the dc-blocking ?lters is selected and if the enable bit of the delay timer is on (en_delay_dblin = sadc_ctrl_deci[21]): ? en_delay_dblin off: t = 0 s ? dc ?lter 1 is off, dc ?lter 2 is off and en_delay_dblin is on: t = 44/f s ; t = 1 ms at f s = 44.1 khz ? dc ?lter 1 is on, dc ?lter 2 is off and en_delay_dblin is on: t = 17066/f s ; t = 387 ms at f s = 44.1 khz ? dc ?lter 2 is on and en_delay_dblin is on: t = 67473/f s ; t = 1.53 s at f s = 44.1 khz. interpolation ?lter pass band ripple up to 0.4535f s 0.02 db stop band from 0.5465f s - 72 db gain pass band - 1.1 db dynamic range up to 0.4535f s >143 db fig 8. decimator data path table 17: filter characteristics continued description conditions value unit 001aab457 128f s comb 8f s dc hpf1 1f s 1f s dc hpf2 8f s sound features halfband dsp vol. ctrl 8f s hb3 4f s hb2 2f s hb1
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 38 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.19.2.3 soft start-up after reset after a reset of the decimation ?lter and if bit en_dblin (sadc_ctrl_deci[21]) is a logic 1, the output gain of the decimator is increased from mute to - 63.5 db and at a rate of 0.5 db per f s period to 0 db (db linear) to avoid harsh audible plops. the time required for a complete soft start-up if bit en_dblin is a logic 1 for 128 f s periods. this time is without the time required if bit en_delay_dblin (sadc_ctrl_deci[21]) is a logic 1, e.g. if bit en_dblin and bit en_delay_dblin are a logic 1, bit en_dcfilti and bit en_dcfilto are logic 0 the total time required is (44 +128) f s periods (see t ab le 18 ). the decimator soft start-up function is illustrated in figure 9 . 7.19.2.4 signal polarity the polarity of the output signal is controlled by bit en_pol_inv (sadc_ctrl_deci[17]). when this bit is enabled, the polarity of the output data is inverted. table 18: required time after reset en_delay_dblin en_dblin en_dcfilti en_dcfilto required time 0 0 xx0 s 0 1 x x 128 periods of f s 1 0 0 0 44 periods of f s 1 0 1 0 17066 periods of f s 1 0 x 1 67473 periods of f s 1 1 0 0 (44 + 128) periods of f s 1 1 1 0 (17066 + 128) periods of f s 1 1 x 1 (67473 + 128) periods of f s for readability, the parallel output data is shown in its analog representation. fig 9. soft start-up function 001aab463 44 periods of f s 128 periods of f s a ble_delay_dblin = 1 dout (analog representation) enable_dblin = 1 reset = 0 en_dcfilto = 0 en_dcfilti = 0
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 39 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.19.2.5 mute when the left and right channel of the decimator are muted (bit en_mute is a logic 1), the gain in the decimator is decreased linearly to - 63.5 db with a ?nal step to mute at a rate of 0.5 db per f s period (db linear). this is done to avoid harsh audible plops. the time required for a complete mute depends on the initial gain setting. maximum required time is 256 f s periods. when a complete mute is achieved for both left and right channels, the bit mute_state (sadc_ctrl_deco[0]) is made logic 1. when the channels are de-muted (bit en_mute is a logic 0) the gain of the decimator is increased at the same rate until the programmed gain setting is achieved. 7.19.2.6 over?ow detection the output signal is used to indicate whenever the output data, in either the left or right channel, is larger than - 1.16 db of the maximum possible digital swing. when this condition is detected the over?ow bit (sadc_ctrl_deco[1]) is forced to a logic 1 for at least 512 f s cycles (11.6 ms at f s = 44.1 khz) allowing even a slow microcontroller to poll this event. this time-out is reset for each infringement. 7.19.2.7 agc function the decimation ?lter is equipped with an automatic gain control (agc) block. this function is intended, when enabled, to keep the output signal at a constant level. the agc can be used for microphone applications in which the distance to the microphone is not always the same. the agc can be enabled via the control register (sadc_ctrl_deci[23]). in this case it bypasses the digital volume control. other features of the agc, such as the attack, decay and target level can be set via the same register. the dc ?lter in front of the decimation ?lter must be enabled when agc is in operation, otherwise the output will be disturbed by the dc offset added in the adc. table 19: agc enable control agc_en agc function 0 disabled, manual gain control via the left/right decimator volume control, (default) 1 enabled, with manual microphone gain settings via pga table 20: agc target level settings agc_level1 agc_level0 agc target level value (db) 00 - 5.5 01 - 8.0 10 - 11.5 11 - 14.0
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 40 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.20 audio output 7.20.1 sdac the stereo digital-to-analog converter (sdac) is a module with interpolation ?lters and noise shaper for low frequency applications such as audio and tv-audio. in this section the analog and digital part is described. the digital part consists of an interpolation ?lter that increases the sample rate from 1f s to 128f s and a third order noise shaper that runs on 128f s or 256f s . the inputs to the sdac are two 24-bit parallel input words, left and right, and a synchronization signal (din_valid) at f s (f s , the sample rate, is typically 44.1 khz). the output is a stereo analog signal (vout_linel and vout_liner). 7.20.1.1 features of the sdac ? 24-bit data path with 16-bit coef?cients ? full fir ?lter implementation for all of the upsampling ?lter ? digital db-linear volume control in 0.25 db steps ? digital de-emphasis for 32 khz, 44.1 khz, 48 khz and 96 khz ? selection for the 2f s to 8f s upsampling ?lter characteristics (sharp/slow-roll-off) ? support for 2f s and 8f s input signals: C 1f s with full feature support, being de-emphasis, master volume control and soft mute C 2f s input with master volume and mute support: required for double speed mode C 8f s input no features supported. this is intended for dsd support (grabbing data at 8f s from an external dsd unit) ? soft mute with a raised cosine function ? controlled power-down sequence comprising a raised cosine mute function followed by a dc ramp down to zero to avoid audible plops or clicks ? integrated digital silence detection for left and right with selectable silence detection time ? polarity control table 21: agc time constant settings agc_time2 agc_time1 agc_time0 agc setting 44.1 khz sampling 8 khz sampling attack time (ms) decay time (ms) attack time (ms) decay time (ms) 00011 100 61 551 00116 100 88.2 551 01011 200 61 1102 01116 200 88.2 1102 10021 200 116 1102 10111 400 61 2205 11016 400 88.2 2205 11121 400 116 2205
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 41 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband ? simple switched resistors architecture ? data-weighted averaging technique reducing distortion ? large supply voltage range (0.8 v to 3.6 v) ? low noise (n > 100 dba). 7.20.1.2 functional description the sdac comprises the following functions: ? sound feature processor ? digital upsampling ?lter ? noise shaper ? dac. digital de-emphasis can be set by a 3-bit control bus (bits ctrl_inti[18:16]) for the range of sample frequencies available (32 khz, 44.1 khz, 48 khz and 96 khz). the de-emphasis ?lters are only in the signal path for normal speed mode (data input at 1f s ). in the interpolation ?lter a three stage linear digital volume control is provided with a range from 0 db to - 89 db and - db. down to the attenuation of - 50 db the step size equals 0.25 db, from - 50 db to - 83 db it equals 3 db and the last step to - 89 db is one of 6 db. the attenuation for the left channel is controlled by bits ctrl_inti[15:8]; the attenuation for the right channel is controlled by bits ctrl_inti[7:0]. when the left and right channels of the interpolator are muted (bit ctrl_inti[19] = 1), the gain in the interpolator is decreased to - db conforming to a raised cosine function to avoid harsh audible plops (soft mute). this mute function is completed after a period of 128 samples in normal mode i.e. 2.9 ms at f s = 44.1 khz. when a complete mute is achieved for both left and right channels, the bit ctrl_into[0] is made a logic 1. the interpolator mute function is illustrated in figure 11 . fig 10. block diagram of the sdac 001aab465 SAA8200HL sound control interpolation filter and noiseshaper hp dac v dd din_l [ 23:0 ] din_r [ 23:0 ] din_valid dac hp_outl dac_outl hp_outc hp_outr dac_outr 16 14 18 20 15 v dda(3v3_dac) v dac_refn v dac_refp v ss
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 42 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.20.1.3 power-down when the interpolator is powered down (bit ctrl_inti[25] = 1), the gain in the interpolator is decreased to - db to conform to a raised cosine function. this is followed by a dc ramp down to zero output data (000000h). the slope of this dc ramp can be set by bit ctrl_inti[24] to either 512 f s periods (default) or 1024 f s periods. the power-up follows the reverse procedure, a dc ramp up to mid scale plus dc dither (2 to [6 + 2] to [10 + 2] to 17) followed by a gain increase to conform to a raised cosine function. total fig 11. interpolator mute signals 001aab466 raised cosine roll-off (128 periods of f s ) t rl_into [ 0 ] (mute state) ctrl_inti [ 19 ] (mute) interpolator 4-bit output data (analog representation) fig 12. interpolator power-up and power-down sequence 001aab467 raised cosine roll-off (128 periods of f s ) dc ramp down (512 periods of f s ) t rl_into [ 0 ] (mute state) ctrl_inti [ 25 ] ctrl_into [ 1 ] interpolator 4-bit output data (analog representation) 640 periods of f s
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 43 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband time required for a full power-up or power-down equals 128 f s periods (raised cosine function) plus 512 f s periods (dc ramp up/down) making 640 f s periods or 14.5 ms for f s = 44.1 khz. the power-up and power-down function is illustrated in figure 12 . 7.20.1.4 silence detection the silence detection circuit counts the number of digital input samples equal to zero. it is enabled by the control bit ctrl_inti[30]. the number of zero samples before signalling silence detected (bit ctrl_into[3] for left channel and bit ctrl_into[2] for right channel) can be set by bits ctrl_inti[29:28]. this feature is not used to control the sdac, it is simply a feature that can be used in the system. 7.20.1.5 polarity control the stereo output signal polarity of the c18int can be changed by setting the ctrl_inti[26] to logic 1. note that this single control bit affects both channels. 7.20.1.6 digital upsampling ?lter the interpolation from 1f s to 128f s is realized in four stages: ? the ?rst stage is a 99-tap half band ?lter (hb) which increases the sample rate from 1f s to 2f s and has a steep transition band to correct for the missing inherent ?lter function of the sdac. ? the second stage is a 31-tap fir ?lter which increases the data rate from 2f s to 8f s , scales the signal and compensates for the roll-off caused by the sample-and-hold function prior to the noise shaper. for this ?lter three sets of coef?cients can be chosen realizing three different transfer characteristics. ? the third stage is a simple hardware linear interpolator (lin) function that increases the sample rate from 8f s to 16f s and removes the 8f s component in the output spectrum. the main reason for upsampling to 16f s is the fact that the sdac only has a ?rst order roll-off function. ? the fourth and last stage is a sample-and-hold function increasing the sample rate from 16f s to a selectable 128f s or 256f s , depending on the actual input data rate. for input sample rates between 8 khz and 32 khz the noise shaper and dac must run on 256f s instead of the typical 128f s to avoid a signi?cant noise increase in the audible frequency band of 0 khz to 20 khz. fig 13. interpolator data path 001aab468 normal speed double speed dsd deem 2 hb mt vc s&h lin 4 fir 1f s 2f s 8f s 16f s 128f s or 256f s 2f s 8f s
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 44 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband the sdac has three modes of operation which are set by the control input bits ctrl_inti[21:20]: ? normal 1f s input mode used for input data rates between 8 khz and 96 khz using sharp ?lter roll-off. de-emphasis (deem), volume control (vc) and mute (mt) functions are all available in this mode ? 2f s input mode which may be used as: C double speed input when the data rate is between 96 khz and 200 khz C a means to get slow roll-off by skipping the ?rst half band ?lter (hb). in this mode the de-emphasis (deem) is not available ? 8f s or dsd input mode, in which case the input is obtained form an external dsd block. de-emphasis (deem), volume control (vc) and mute (mt) features are unavailable in this mode. 7.20.1.7 noise shaper the 3rd-order noise shaper operates at either 128f s or 256f s depending on the mode of operation de?ned by bits ctrl_inti[23:20]. it shifts in-band quantization noise to frequencies well above the audio band. this noise shaping technique enables high signal-to-noise ratios to be achieved at low frequencies. the noise shaper output is converted into an analog signal using a 4-bit switched resistor digital-to-analog converter. 7.20.1.8 sdac the 4-bit sdac is based on a switched resistor architecture which is merely a controlled voltage divider between the positive and negative reference supplies vref_dacp and vref_dacn . the 4-bit input data from the noise shaper is ?rst decoded to a 15 level thermometer code controlling the 15 taps of the converter. added to the decoding is a selectable data weighted averaging (dwa) technique which guarantees that there is no correlation between the input signal and the resistors used for that input signal. after decoding and dwa the buffers connect the resistors to either the vref_dacp or vref_dacn . in doing this the reference voltage will be divided depending on the input signal. the result is an analog output voltage with a rail-to-rail maximum output swing. the output impedance of this dac is approximately 1 k w . by applying an external capacitor of 3.3 nf to the line output (voutlinel or vout_liner) a low pass post ?lter is introduced with a - 3 db roll off at 48 khz (dimensioned for f s = 44.1 khz). this will thus reduce the 3rd order noise shaped output spectrum of the dac to a noise spectrum increasing with 2nd order. the value of this capacitor depends on the actual sample frequency used. 7.20.1.9 data weighting averaging the sdac features two dwa algorithms which can be selected independently for the left (bit ctrl_dac[1]) and right (bit ctrl_dac[0]) channels. by setting these bits to a logic 0 the uni-directional dwa algorithm is chosen which is best suited for good s/n ?gures. by setting these bits to a logic 1 the bi-directional dwa algorithm is chosen which is best for low distortion.
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 45 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.20.2 headphone 7.20.2.1 headphone driver the headphone driver can deliver 22 mw (at 3.0 v power supply) into16 w load. the headphone driver does not need external dc decoupling capacitors because it can be dc-coupled with respect to a special headphone output reference voltage. this saves two external capacitors. changes in the load on the dac outputs in?uence the output of the headphone. this is because the headphone inputs are directly connected to the dac outputs. 7.20.2.2 headphone limiter to protect the headphone ampli?er from serious damage due to short-circuiting of the outputs (e.g. during the connection of a headphone jack plug) a current limiter is incorporated. the activation of this current limiter is signaled by individual logic clip signals ( clip_l , clip_r and clip_c ). the level at which the current limiter is activated can be set to four different levels for each ampli?er. the current level to which the output stage is limited can be set with the bits set_limiter_l/r/c[1:0] inputs from 80 ma to 140 ma for the left and right channels and from 180 ma to 240 ma for the common channel (see t ab le 22 ). the maximum current for the common ground channel is larger (double on average) as this channel must be able to sink and source the left and right channel output currents. when the current through the output stage exceeds the programmed current level, the monitor bit clip_l, clip_r or clip_c is set to a logic 1 and the output stage is shut down. these values are based on the worst case situation of two in-phase full scale input signals of 1.0 v (rms) and a minimum headphone impedance of 16 w . this results in left and right channel peak output currents of 1.41 v / 16 w = 88.4 ma and a common ground peak output current of 2 88.4 ma = 176.8 ma. the maximum current that is actually ?owing in the common ground ampli?er is always the sum of the left and right channel maximum currents. table 22: output current limiter settings set_limiter_l[1:0], set_limiter_r[1:0], set_limiter_c[1:0] maximal output current left and right channel common channel 00 off off 01 100 ma (default) 200 ma (default) 10 120 ma 220 ma 11 140 ma 240 ma
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 46 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.21 dc-to-dc converter the SAA8200HL needs two supply voltages, 3.3 v for analog functions and 1.7 v for digital functions. for normal operation one or two batteries of 1.5 v will be used as an energy source, from which the dc-to-dc converter must generate the required voltage levels, see figure 14 . two inductive dc-to-dc converters will be used when the chip is battery operated. the v dde pins are externally connected to pin dcdc_out3v3, the v ddi pins are connected to pin dcdc_out1v8. when the SAA8200HL is supplied from usb, the outputs of the dc-to-dc converters will be overruled by two linear regulators. in that case the supply voltages will be 3.3 v and 1.8 v. this is independent from the usb voltage (4.0 v to 5.5 v) so a reference circuit is needed. during the start-up sequence the dc-to-dc controller uses the ring osc to control the switching regulators. after start-up the 12 mhz from the digital core is fed to the dc-to-dc controller. in battery operation mode the output voltage dcdc_out1v8 and dcdc_out3v3 can be controlled by three adjust bits. care has to be taken with signal levels (level shifters) and the start-up and shut-down from battery to usb and from usb to battery transitions. a delay circuit uses ring osc clocks to generate a delay of about 1 ms for the reset_b pulse. in usb mode the delay can be generated otherwise. the dc-to-dc converter has to operate from a single or from two batteries. this has no consequence for the ?rst dc-to-dc converter, this is always an up converter. in case a single battery is used the second converter is also an up converter but it is a down fig 14. dc-to-dc converter block schematic 001aac002 dc vin vusb_present vout dc ldo1 linear regulator 1 switching regulator 1 dc dc switching regulator 2 vref low voltage bandgap analog dc to dc - controller digital delay por pll 12 mhz adjust digital core xosc ring osc vdd_always v bat(dcdc) < 1.6 v v bat(dcdc) v usb(dcdc) dcdc_out3v3 dcdc_out1v8 vin vout ldo2 linear regulator 2
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 47 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband converter when two batteries are used. pin downsel selects the type of converter and thus how many batteries are connected. if pin downsel is high the SAA8200HL operates from two batteries and the second dc-to-dc converter is a down converter. if pin downsel is low the SAA8200HL operates from one battery and the second dc-to-dc converter is an up converter, see figure 15 7.21.1 controller the controller consists of an analog and a digital part. the analog part compares the output voltage vout[1,2] with a programmable voltage window in eight possible adjust settings. the digital part computes the switching time such that the output voltage stays within this window. in the analog part is one restive divider with a programmable output, see figure 16 . together with reference voltage v ref the voltage window is de?ned. the output of the resistive divider is compared to the reference voltage with comparators with added offset. the outputs vth (voltage too high) and vtl (voltage too low) are based on the comparison. when vth is asserted means that vin is higher than the upper limit of the window, indicating to the digital part of the controller that the output voltage must be lowered. when vtl is asserted it indicates that vin is lower than the lower limit of the window, indicating to the digital part of the controller that the output voltage must be higher. when neither is asserted, vin is between the lower and upper limit of the window, indicating to the digital part of the controller that the output voltage is in the limits of the window and it does not have to change the output voltage. this is the normal mode of operating and is called continuous mode because the coil continuously carries current. in continuous mode the digital part of the controller generates switching cycles at a ?xed frequency. during the ?rst part of such a cycle (t1) switch 1 will be closed and switch 2 will be opened, during the last part of the cycle (t2) switch 2 will be closed and switch 1 will be opened. the length of t1 as a fraction of the cycle time is set such that the required output voltage is generated. when the output voltage runs outside the window this length is updated such that the output voltage falls within the window again. fig 15. up and down converter topology 001aac003 dcdc_out v ss dcdc_sw dcdc_lx upconverter downconverter v bat(dcdc) dcdc_out v ss dcdc_sw dcdc_lx v bat(dcdc)
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 48 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband see figure 17 for a coil current cycle in continuous mode. the average coil current is equal to the average current demanded by the load. the lengths of t1 and t2 are determined by the battery voltage and the output voltage of the dc-to-dc converter. the output voltage is allowed to vary within a certain window. this means that there will be a voltage ripple with a frequency that is largely correlated to the frequency content of the load current. the peak-to-peak amplitude of the ripple will be more or less equal to the window height. there will be ripple at the switching frequency too, this is mainly caused by the fact that the coil current will run through parasitic resistances of the load circuit. fig 16. analog part of the controller fig 17. coil current cycle in continuous mode 001aac004 comparator v bat(dcdc) bias clk dcdc[1,2]_adjust[2 vout[1,2] vth[1,2] vtl[1,2] v ss v ref v ss(clean) decoding comparator 7 001aac005 t1 t2 t1 t2 t1 t (s) i l (a)
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 49 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband see figure 18 for a coil current cycle in ramp-up mode. the controller enters this mode when there is an increased demand for energy (voltage falls to below the lower limit). by a one-time increase of t1 the coil current is increased to a higher average. see figure 19 for a coil current cycle in discontinuous mode. in this mode the coil current does not ?ow continuously. dependent on energy demand a cycle is generated. so instead of changing the duty cycle as in continuous mode the frequency is changed. this mode is intended for low power operation. during the ?rst phase the battery ramps up the current from zero and during the second phase it is ramped down to zero by the load. the coil current is made to decrease to zero by opening both switches shortly before the current reaches zero. the moment when the switches are to be closed is learned from the behavior of the dc-to-dc converter in continuous mode. fig 18. coil current cycle in ramp-up mode fig 19. coil current cycle in discontinuous mode 001aac006 t1 t2 t1 t2 t1 t2 t1 t2 t2 t1 t (s) t (s) i l (a) 001aac007 t1 t2 t1 t2 t (s) i l (a)
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 50 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband the digital part of the controller consists of a state machine that enables the controller to switch modes. a decision to jump to a different state is taken on the basis of the outputs of the analog part. as a result of some of the jumps, the duration of the ?rst phase of the cycle is increased or decreased, see figure 20 . 7.21.2 linear regulators the linear regulators will be implemented as low drop voltage output (ldo) regulators for a ?xed output voltage, see figure 21 . one ldo has to handle input signals in the order of 5.0 v so a special construction with thick gate oxide is needed. the other ldo handles an input signal of 3.3 v thus a normal construction with thick gate oxide is suf?cient. for the loop stability the choice is made that the dominant pole lies externally. the series resistance of cext (esr) gives a zero and degrades the stability and thus limited to a maximum value. for an accurate output voltage a reference voltage is needed. this voltage can be made with a band gap circuit. a fraction of the output voltage is fed back to the operation ampli?er. in stop mode the ldos should be stable to deliver only small currents. the controller will be in discontinuous mode if adjusted dcdc_out1v8 v bat(dcdc) . no forward diode from v bat(dcdc) to dcdc_out1v8 allowed. fig 20. digital part of the controller 001aac008 sample vth dec. t1 vth discontinuous mode vth sample vtl and vth continuous mode vtl vtl sample vtl inc. t1 ramp-up mode inc. t1 the on terminal is connected to vusb_present. fig 21. principle of ldo 001aac009 self-biased operational amplifier cext capacitor v ss dcdc_out v ss(clean) pcb star ground esr v in o n e f
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 51 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.21.3 timing speci?cation 7.21.3.1 play and stop with battery supply a negative edge at pin dcdc_play starts the dc-to-dc converter, see figure 22 . when minimum supply voltages are detected for dcdc_out1v8 and dcdc_out3v3 by the por, the signal supply_ok is made logic 1. after about 1 ms signal reset_b becomes logic 1. when the supply voltages are correct the voltages to the application control switches rises from v bat(dcdc) to dcdc_out3v3. new negative edges on pin dcdc_play has no in?uence. when pin dcdc_stop becomes high the dc-to-dc converter stops and directly the signal supply_ok becomes a logic 0. the reference circuit, ring oscillator and the por will be fed by v dd(always) . signal reset_b stays at logic 0 for about 1 ms for proper reset. not shown in figure 22 is signal clk_stable, showing the moment for the core clock to become available to the dc-to-dc converters. as soon as a stable core clock is detected the dc-to-dc converters will switch to this clock in order to be in-phase with the dac clock, which will minimize interference into the audio signal. the SAA8200HL is started up when this has happened. fig 22. play and stop with battery supply v bat(dcdc), dcdc_out3v3 0 dcdc_play dcdc_on supply_ok reset_b ~ 1 ms playdet dcdc_stop 001aac010
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 52 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.21.3.2 play and stop with usb supply a start-up from the usb supply gives also a reset_b pulse, see figure 23 . the signal vusb is shaped by the bonding pad supplies v ddi and v dde . the disconnection of v usb(dcdc) generates a stop pulse. fig 23. play and stop with usb supply reset_b supply_ok 0 ~ 1 ms stop usb_det (internal iwab signal) "v usb " v usb_present v usb(dcdc) dcdc_o 001aac011
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 53 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 7.21.3.3 change from battery to usb supply figure 24 shows the timing diagram with a wireless transceiver changed to usb supply. the usb supply has the priority. when the usb plug is disconnected the device goes to the off state. in idle mode the supplies dcdc_out1v8 and dcdc_out3v3 has still to be present, but the ldos have to deliver only a small current. the total device may not draw more than 500 ma from the usb supply so a quiescent current of the few active circuits has to be less then 100 ma each. fig 24. change from battery to usb supply reset_b supply_ok 0 0 dcdc_on dcdc_out3v3 dcdc_out1v8 supply transients from dcdc to ldo and ldo to off dcdc_out3v3 and dcdc_out1v8 stop play playdet usb_det (internal iwab signal) "v usb " v usb _ present v bat(dcdc) v usb(dcdc) 001aac012
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 54 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 8. limiting values [1] equivalent to discharging a 100 pf capacitor via a 1.5 k w series resistor. [2] equivalent to discharging a 200 pf capacitor via a 0.75 m h series inductor. 9. thermal characteristics table 23: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v ddi core supply voltage (internal) - 0.5 2.5 v v dde core supply voltage (external) - 0.5 4.6 v v dda(1v8) 1.8 v supply voltage - 0.5 2.5 v v dda(3v3) 3.3 v supply voltage - 0.5 4.6 v v i input voltage normal digital input pins - 0.5 v dde + 0.5 v 5 v tolerant digital input pins - 0.5 6.0 v analog input pins - 0.5 v dda3v3 + 0.5 v pin xtalh_in - 0.5 2.0 v t amb ambient temperature - 20 +70 c t j junction temperature - 40 +125 c t stg storage temperature - 65 +125 c t xtal crystal temperature - 150 c v bat(dcdc) battery voltage single battery 0.9 1.6 v double battery 1.8 3.2 v v usb(dcdc) usb voltage range 4.0 5.5 v v esd electrostatic discharge voltage [1] v [2] v table 24: thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air k/w
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 55 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 10. characteristics [1] accounts for 100 mv voltage drop in all supply lines. [2] allowed for a short time period. table 25: supply voltage characteristics symbol parameter conditions min typ max unit v ddi core supply voltage (internal) 1.7 1.8 2.0 v v dde core supply voltage (external) mpmc pins 1.7 3.3 3.6 v other 2.7 3.3 3.6 v v dda(1v8_xtalh) crystal oscillator supply voltage 1.7 1.8 2.0 v v dda(3v3_spdif) spdif supply voltage 3.0 3.3 3.6 v v dda(3v3_adc10b) control adc supply voltage 2.7 3.3 3.6 v v dda(1v8_adc) audio adc supply voltage 1.7 1.8 2.0 v v dda(3v3_adc) audio adc supply voltage 2.7 3.3 3.6 v v dda(3v3_dac) audio dac supply voltage 2.7 3.3 3.6 v v dda(3v3_hp) headphone supply voltage 2.7 3.3 3.6 v v usb(dcdc) usb supply voltage 4.0 5.0 5.5 v table 26: 5 v tolerant cells characteristics symbol parameter conditions min typ max unit input circuits v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v v hys hysteresis voltage 0.4 - - v output circuits v oh high-level output voltage i oh depends on i/o cell type [1] v dde - 0.4 - - v v ol low-level output voltage i ol depends on i/o cell type [1] - - 0.4 v i oh high-level output current 10 ns slew rate output; v oh =v dde - 0.4 v [1] - 5--ma i ol low-level output current 10 ns slew rate output; v ol = 0.4 v [1] 4--ma i sc(h) high-level short circuit current 10 ns slew rate output; v oh =0v [2] -- - 45 ma i sc(l) low-level short circuit current 10 ns slew rate output; v ol =v dde [2] - - 50 ma table 27: control adc characteristics symbol parameter conditions min typ max unit v refn negative reference voltage v ssa -v refp - 2v v refp positive reference voltage v refn + 2 - v dda v f smpl sampling rate 400 - 1500 khz z i input impedance refn to refp 20 - 39 k w v i input voltage v refn -v refp v f clk clock frequency - - 4.5 mhz
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 56 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband [1] set headphone ampli?er in power-down mode before setting audio dac in power-down mode because the line output is connected t o the headphone driver the output of the headphone clips towards its analog supply. [2] exclusive the input load of the headphone driver which is 10 k w . [3] the output of the dac is already connected with the headphone driver which has an input load of 10 k w . n resolution 2 - 10 bit inl integral non-linearity - - 1 lsb dnl differential non-linearity - - 1 lsb e os offset error - 20 - +20 mv e fs full scale error - 20 - +20 mv t conv conversion time - (n + 1) cycles - table 27: control adc characteristics continued symbol parameter conditions min typ max unit table 28: static audio characteristics symbol parameter conditions min typ max unit audio dac v refn negative reference voltage - v ssa(dac) -v v refp positive reference voltage - v dda(3v3_dac) -v v o output voltage digital silence - 0.5v dda(3v3_dac) -v during power-down [1] -0 -v r o output resistance [2] 0.7 1 1.3 k w r l load resistance [3] >75 - - k w r int resistance between v refp and v refn -4 -k w headphone ampli?er v hp_com reference input voltage - 0.5v dda(3v3_vrefp) -v v o(cm) common mode output voltage - v i(ref) -v v offset input offset voltage - 10 - +10 mv r l load resistance 16 - - w i sc output current at short circuit left and right 80 100 140 ma center 180 200 240 ma audio adc v adc_refp positive reference voltage - v dda(3v3_adc) -v v adc_refn negative reference voltage - 0 - v v adc_com common mode reference voltage - 0.5v dda(3v3_adc) -v r i input resistance - 12 - k w c i input capacitance - 24 pf low noise ampli?er r i input resistance 3.5 5 - k w v offset output offset voltage - - 1 mv
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 57 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband table 29: dynamic audio characteristics v dda(3v3) = 3.3 v; f i = 1 khz at - 1 db; t amb =25 c; r l = 100 k w ; f s = 48 khz; all voltages measured with respect to ground; unless otherwise speci?ed. symbol parameter conditions min typ max unit audio dac v o(rms) output voltage (rms value) at 0 dbfs digital input; [1] -1 -v d v o unbalance between channels - <0.1 - db v o output voltage digital silence - 0.5v dda(3v3_dac) -v during power-down [1] -0 -v (thd+n)/s total harmonic distortion-plus-noise to signal ratio at 0 db - - 80 - db at - 60 db; a-weighted - - 40 - db s/n signal-to-noise ratio code = 0; a-weighted; bidirectional dwa - 100 - db a cs channel separation - 90 - db headphone ampli?er p o(rms) output power (rms value) at 0 dbfs digital input; r l =16 w -35 -mw (thd+n)/s total harmonic distortion-plus-noise to signal ratio at 0 db; r l = 16 w -62 - 52 db at 0 db; r l = 5 k w -82 -db at - 60 db; a-weighted - 35 - db s/n signal-to-noise ratio code = 0; a-weighted - 97 - db a cs channel separation r l = 16 w - no decoupling capacitors - - 36 - db with decoupling capacitors - - 90 - db audio adc d v i unbalance between channels -<1 -db s/n signal-to-noise ratio v i = 0 v; a-weighted - 95 - db a cs channel separation - 110 - db psrr power supply rejection ratio f ripple = 1 khz; v ripple(p-p) =30mv v dda(3v3_adc) - - 55 - db v dda(3v3_refp) - - 65 - db d o digital output level 0 db setting; v i(rms) = 1.0 v - 2.5 - 1 - 1 dbfs 3 db setting; v i(rms) = 708 mv - 2.5 - 1 - 1 dbfs 6 db setting; v i(rms) = 501 mv - 2.5 - 1 - 1 dbfs 9 db setting; v i(rms) = 354 mv - 2.5 - 1 - 1 dbfs 12 db setting; v i(rms) = 252 mv - 2.5 - 1 - 1 dbfs 15 db setting; v i(rms) = 178 mv - 2.5 - 1 - 1 dbfs 18 db setting; v i(rms) = 125 mv - 2.5 - 1 - 1 dbfs 21 db setting; v i(rms) =89mv - 2.5 - 1 - 1 dbfs 24 db setting; v i(rms) =63mv - 2.5 - 1 - 1 dbfs
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 58 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband [1] the output voltage of the dac is proportional to the dac power supply voltage and the headphone is in power-down mode. [2] exclusive the input load of the headphone driver which is 10 k w . [3] the output of the dac is already connected with the headphone driver which has an input load of 10 k w . (thd+n)/s total harmonic distortion-plus-noise to signal ratio at - 1 dbfs 0 db setting - - 85 - db 3 db setting - - 87 - db 6 db setting - - 88 - db 9 db setting - - 88 - db 12 db setting - - 87 - db 15 db setting - - 85 - db 18 db setting - - 83 - db 21 db setting - - 80 - db at - 60 dbfs 0 db setting - - 35 - db 3 db setting - - 34 - db 6 db setting - - 32 - db 9 db setting - - 30 - db 12 db setting - - 28 - db 15 db setting - - 26 - db 18 db setting - - 23 - db 21 db setting - - 20 - db 24 db setting - - 20 - db lna plus adc v i(rms) input voltage (rms value) at 0 dbfs digital output; r s = 2.2 k w - - 35 mv (thd+n)/s total harmonic distortion-plus-noise to signal ratio v o = 600 mv - - 75 - db at - 60 db; a-weighted - - 25 - db s/n signal-to-noise ratio v i = 0 v; a-weighted - 85 - db table 29: dynamic audio characteristics continued v dda(3v3) = 3.3 v; f i = 1 khz at - 1 db; t amb =25 c; r l = 100 k w ; f s = 48 khz; all voltages measured with respect to ground; unless otherwise speci?ed. symbol parameter conditions min typ max unit table 30: dc-to-dc converter characteristics symbol parameter conditions min typ max unit v bat battery voltage single battery 0.9 1.35 1.6 v double battery 1.8 2.7 3.2 v v usb usb voltage 4.0 5.0 5.5 v dc-to-dc converter for 3.3 v v o output voltage 3.0 3.4 3.7 v v o(tol) output voltage tolerance - - 100 mv
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 59 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband i o output current v bat = 2.4 v; r l = 0.3 w 200 - - ma v bat = 2.0 v; r l = 0.3 w 150 - 200 ma i su start-up current - - 25 ma i sw switch current - -ma f switch switching frequency - - 1 mhz f clk clock frequency - - 12 mhz h ef?ciency v bat = 2.4 v; i o = 100 ma; r l = 0.3 w 90 93 - % r p pmost switch on resistance - 0.3 - w r n nmost switch on resistance - 0.3 - w esr c maximum esr c - - 0.7 w dc-to-dc converter for 1.8 v v o output voltage 1.3 1.85 2.0 v v o(tol) output voltage tolerance - - 50 mv i o output current v bat = 2.4 v; r l = 0.3 w 100 - - ma v bat = 2.0 v; r l = 0.3 w 50 - 200 ma i su start-up current - - 10 ma i sw switch current - -ma f switch switching frequency - - 1 mhz f clk clock frequency - - 12 mhz h ef?ciency v bat = 2.4 v; i o =50ma; r l = 0.3 w 92 95 - % r p pmost switch on resistance - 0.9 - w r n nmost switch on resistance - 0.9 - w esr c maximum esrc - - 0.7 w low-drop-out converter for 3.3 v v o output voltage unloaded - 3.5 - v i o = 100 ma - 3.4 - v v o(tol) output voltage tolerance - - 100 mv i o output current v usb = 5 v 150 - 200 ma i idle idle current - - 100 m a low-drop-out converter for 1.8 v v o output voltage unloaded - 1.95 - v i o = 50 ma - 1.85 - v v o(tol) output voltage tolerance - - 50 mv i o output current v usb = 5 v 50 - 100 ma table 30: dc-to-dc converter characteristics continued symbol parameter conditions min typ max unit
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 60 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband ring oscillator i dda current consumption - - 100 m a f osc oscillator output frequency - 12 - mhz table 30: dc-to-dc converter characteristics continued symbol parameter conditions min typ max unit table 31: sri characteristics symbol parameter conditions min typ max unit lvds buffer static i dda supply current - 150 - m a i dda(pd) power-down supply current - - 1 m a c l load capacitor - - 5 pf r o output voltage as ratio of the digital supply voltage - 0.25 - v i(det) input voltage required for detection - 100 - mv dynamic f clk(max) maximum clock frequency - - 1 mhz table 32: timing characteristics symbol parameter conditions min typ max unit crystal oscillator static c i(xtalh_in) parasitic input capacitance pin xtalh_in pf r i(xtalh_in) parasitic input resistance pin xtalh_in f i =12mhz w p drive crystal level of driver power 100 - 500 m w dynamic f osc oscillator frequency - 12 - mhz a cl duty cycle - 50 - % t su start-up time - 500 - ms serial interface input and output data timing; see figure 25 f bck bit clock frequency - - 128f s hz t cy(bck) bit clock cycle time t cy(s) is sample frequency cycle time -- 1 128 t cy(s) s t bckh bit clock high time 30 - - ns t bckl bit clock low time 30 - - ns t r rise time - - 20 ns t f fall time - - 20 ns t su(ws) word select setup time 10 - - ns t h(ws) word select hold time 10 - - ns t su(i2sin) data input setup time 10 - - ns t h(i2sin) data input hold time 10 - - ns
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 61 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband t h(i2sout) data output hold time 0 - - ns t d(i2sout_bck) data output to bit clock delay - - 30 ns t d(i2sout_ws) data output to word select delay - - 30 ns standard mode i 2 c-bus; sda and scl lines 100 khz mode f scl scl clock frequency 0 - 100 khz t low scl clock low period 4.7 - - m s t high scl clock high period 4.0 - - m s t hd;sta hold time start condition 4.0 - - m s t su;sta setup time start condition 4.7 - - m s t su;sto setup time stop condition 4.0 - - m s t buf bus free time between a stop and start condition 4.7 - - m s t hd;dat data hold time 5.0 - 0.9 m s t su;dat data setup time 250 - - ns t r rise time sda and scl - - 1000 ns t f fall time sda and scl - - 300 ns 400 khz mode f scl scl clock frequency 0 - 400 khz t low scl clock low period 1.3 - - m s t high scl clock high period 0.6 - - m s t hd;sta hold time start condition 0.6 - - m s t su;sta setup time repeated start 0.6 - - m s t su;sto setup time stop condition 0.6 - - m s t buf bus free time between a stop and start condition 1.3 - - m s t hd;dat data hold time 0 - - m s t su;dat data setup time 100 - - ns t r rise time sda and scl 20 + 0.1c b - 300 ns t f fall time sda and scl 20 + 0.1c b - 300 ns t sp pulse width of spikes 0 - 50 ns c b capacitive load for each bus line - - 400 pf table 32: timing characteristics continued symbol parameter conditions min typ max unit
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 62 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband fig 25. serial interface input data timing 001aab634 ws bck i2sin i2sout t f t r t h(ws) t su(ws) t bckh t bckl t cy(bck) t h(i2sout) t su(i2sin) t h(i2sin) t d(i2sout_bck) t d(i2sout_ws) table 33: filter characteristics description conditions value unit decimation ?lter pass band ripple up to 0.45f s 0.02 db stop band from 0.55f s - 60 db overall gain dc 3 db dynamic range up to 0.45f s 140 db droop at 0.45f s - 0.18 db dc blocking ?lter 1 pass band ripple none db pass band gain 0 db droop at 0.00045f s 0.5 db dc attenuation > 40 db dynamic range up to 0.45f s > 110 db dc blocking ?lter 2 pass band ripple none db pass band gain 0 db droop at 0.00045f s 0.031 db dc attenuation > 40 db dynamic range up to 0.45f s > 110 db interpolation ?lter pass band ripple up to 0.4535f s 0.02 db stop band from 0.5465f s - 72 db gain pass band - 1.1 db dynamic range up to 0.4535f s >143 db
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 63 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband fig 26. timing of the i 2 c-bus transfer mbc611 p s sr p sda scl t f t r t buf t low t hd;dat t hd;sta t hd;sta t sp t su;dat t su;sta t su;sto t high
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 64 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 11. application information fig 27. ensation link application diagram i 2 c-bus main system 001aab384 xtalh_in xtalh_out 1.8 v 3.3 v sri_int iic_sri_scl iic_sri_sda sri_data_n sri_data_p sri_fsync_n sri_fsync_p sri_gchclk_n sri_gchclk_p i2sin_1_data i2sin_1_ws i2sin_2_ws i2sin_2_data i2sin_2_bck i2sin_1_bck 92 91 8 100 1 spdif_in spdif_in 29 72 i 2 s-bus1 73 74 76 i 2 s-bus out2 77 i 2 s-bus out1 line out headphone out 79 14 15 78 83 82 81 16 18 20 7 i 2 s-bus2 84 23 line in mic in adc_inr adc_inl adc_mic_in adc10b_gpa3 adc10b_gpa2 adc10b_gpa1 adc10b_gpa0 87 4 channel analog in cmd1 cmd2 cmd3 cmd4 3.3 v 99 98 2 3 uart 26 25 80 i2sout_ws i2sout_bck i2sout_1_data dac_outl dac_outr i2sout_2_data uart_txs uart_rxs uart_ncts hp_outl hp_outc hp_outr adc_mic_lna adc_mic_pga iic_ms_scl v bat (dcdc) dcdc_lx1 dcdc_lx2 dcdc_out3v3 dcdc_out1v8 iic_ms_sda uart_nrts 95 94 97 96 tea7000 saa8200 system par eeprom tx filter app code eeprom v cca(3v3) v bat v bat v ccd(1v8) 56 62 59 61 55 rx filter 24 27 42 41 40 39
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 65 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 12. package outline fig 28. package outline sot407-1 (lqfp100) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot407-1 136e20 ms-026 00-02-01 03-02-20 d (1) (1) (1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e q e a 1 a l p detail x l (a ) 3 b 25 c d h b p e h a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 5 10 mm scale lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 66 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 13. handling information inputs and outputs are protected against electrostatic discharge in normal handling. however, to be completely safe you must take normal precautions appropriate to handling integrated circuits. 14. soldering 14.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 14.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 cto270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results:
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 67 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 14.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c. 14.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. table 34: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, vfbga, xson not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5] [6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 68 of 71 philips semiconductors SAA8200HL ensation base integrated wireless audio baseband [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 15. additional soldering information 15.1 lead-free solder lead-free solder can be used for soldering the tea7000. 15.2 msl level msl level: 16. revision history table 35: revision history document id release date data sheet status change notice doc. number supersedes SAA8200HL_2 20051017 preliminary data sheet - - SAA8200HL_1 modi?cations: ? audio adc supply voltages added ( t ab le 25 ). ? audio dac r l value revised; v hp_com value corrected; v adc_com value added ( t ab le 28 ). ? dynamic audio characteristics revised ( t ab le 29 ). SAA8200HL_1 20041217 objective data sheet - 9397 750 13236 -
philips semiconductors SAA8200HL ensation base integrated wireless audio baseband SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 69 of 71 17. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 19. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 20. trademarks notice all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of koninklijke philips electronics n.v. ensation is a trademark of koninklijke philips electronics n.v. 21. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
philips semiconductors SAA8200HL ensation base integrated wireless audio baseband SAA8200HL_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 02 17 october 2005 70 of 71 continued >> 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 functional description . . . . . . . . . . . . . . . . . . 10 7.1 epics7b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.1.1 user registers . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 vpb0 bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2.1 vpb0 bridge address de?nitions . . . . . . . . . . 15 7.3 clock generation unit . . . . . . . . . . . . . . . . . . . 23 7.3.1 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 24 7.3.2 audio pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3.3 system pll . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 serial radio interface. . . . . . . . . . . . . . . . . . . . 25 7.5 sri i 2 c-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.6 system i 2 c-bus interface . . . . . . . . . . . . . . . . 26 7.7 control adc . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.8 watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 26 7.9 reed-solomon codec . . . . . . . . . . . . . . . . . . . 27 7.10 event router . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.11 spdif inputs. . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.12 i 2 s-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.12.1 i 2 s-bus inputs . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.12.2 i 2 s-bus outputs . . . . . . . . . . . . . . . . . . . . . . . . 31 7.13 time stamp counters . . . . . . . . . . . . . . . . . . . 31 7.14 dma controller . . . . . . . . . . . . . . . . . . . . . . . . 32 7.15 i/o con?guration . . . . . . . . . . . . . . . . . . . . . . . 32 7.16 vpb1 bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.17 uart con?guration. . . . . . . . . . . . . . . . . . . . . 33 7.18 audio con?guration . . . . . . . . . . . . . . . . . . . . . 34 7.19 audio input . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.19.1 adc analog front-end . . . . . . . . . . . . . . . . . . . 34 7.19.1.1 applications and power-down modes . . . . . . . 34 7.19.1.2 lna. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.19.1.3 pga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.19.1.4 applications with 2 v (rms) input . . . . . . . . . 35 7.19.1.5 sdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.19.2 decimation ?lter (adc) . . . . . . . . . . . . . . . . . . 36 7.19.2.1 volume control . . . . . . . . . . . . . . . . . . . . . . . . 37 7.19.2.2 dc blocking ?lter. . . . . . . . . . . . . . . . . . . . . . . 37 7.19.2.3 soft start-up after reset . . . . . . . . . . . . . . . . . 38 7.19.2.4 signal polarity. . . . . . . . . . . . . . . . . . . . . . . . . 38 7.19.2.5 mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.19.2.6 over?ow detection . . . . . . . . . . . . . . . . . . . . . 39 7.19.2.7 agc function . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.20 audio output . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.20.1 sdac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.20.1.1 features of the sdac . . . . . . . . . . . . . . . . . . 40 7.20.1.2 functional description . . . . . . . . . . . . . . . . . . 41 7.20.1.3 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.20.1.4 silence detection . . . . . . . . . . . . . . . . . . . . . . 43 7.20.1.5 polarity control . . . . . . . . . . . . . . . . . . . . . . . . 43 7.20.1.6 digital upsampling ?lter . . . . . . . . . . . . . . . . . 43 7.20.1.7 noise shaper . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.20.1.8 sdac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.20.1.9 data weighting averaging . . . . . . . . . . . . . . . . 44 7.20.2 headphone. . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.20.2.1 headphone driver. . . . . . . . . . . . . . . . . . . . . . 45 7.20.2.2 headphone limiter. . . . . . . . . . . . . . . . . . . . . 45 7.21 dc-to-dc converter . . . . . . . . . . . . . . . . . . . . 46 7.21.1 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.21.2 linear regulators . . . . . . . . . . . . . . . . . . . . . . 50 7.21.3 timing speci?cation . . . . . . . . . . . . . . . . . . . . 51 7.21.3.1 play and stop with battery supply. . . . . . . . . . 51 7.21.3.2 play and stop with usb supply . . . . . . . . . . . 52 7.21.3.3 change from battery to usb supply. . . . . . . . 53 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 54 9 thermal characteristics . . . . . . . . . . . . . . . . . 54 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 55 11 application information . . . . . . . . . . . . . . . . . 64 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 65 13 handling information . . . . . . . . . . . . . . . . . . . 66 14 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 14.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 14.2 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 66 14.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 66 14.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 67 14.5 package related soldering information . . . . . . 67 15 additional soldering information . . . . . . . . . . 68 15.1 lead-free solder . . . . . . . . . . . . . . . . . . . . . . . 68 15.2 msl level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 16 revision history . . . . . . . . . . . . . . . . . . . . . . . 68 17 data sheet status. . . . . . . . . . . . . . . . . . . . . . . 69 18 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 19 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
? koninklijke philips electronics n.v. 2005 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 17 october 2005 document number: SAA8200HL_2 published in the netherlands philips semiconductors SAA8200HL ensation base integrated wireless audio baseband 20 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 21 contact information . . . . . . . . . . . . . . . . . . . . 69

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